 | 2012 |
|---|
| 6 |       | Vibhu Sharma,
Stefan Cosemans,
Maryam Ashouei,
Jos Huisken,
Francky Catthoor,
Wim Dehaene:
Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM.
DATE 2012: 1042-1047 |
| 2011 |
|---|
| 5 | | Bram Rooseleer,
Stefan Cosemans,
Wim Dehaene:
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link.
ESSCIRC 2011: 519-522 |
| 4 | | Anselme Vignon,
Stefan Cosemans,
Wim Dehaene:
A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh.
ESSCIRC 2011: 523-526 |
| 3 | | Vibhu Sharma,
Stefan Cosemans,
Maryam Ashouei,
Jos Huisken,
Francky Catthoor,
Wim Dehaene:
8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes.
ESSCIRC 2011: 531-534 |
| 2 | | Vibhu Sharma,
Stefan Cosemans,
Maryam Ashouei,
Jos Huisken,
Francky Catthoor,
Wim Dehaene:
A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy.
J. Solid-State Circuits 46(10): 2416-2430 (2011) |
| 2009 |
|---|
| 1 | | Anselme Vignon,
Stefan Cosemans,
Wim Dehaene,
Pol Marchal,
Marco Facchini:
A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context.
DATE 2009: 929-933 |
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