Pasquale Corsonello

	2012
47		Fabio Frustaci, Pasquale Corsonello, Stefania Perri: Analytical Delay Model Considering Variability Effects in Subthreshold Domain. IEEE Trans. on Circuits and Systems 59-II(3): 168-172 (2012)
46		Paolo Zicari, Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo: Low-cost FPGA stereo vision system for real time disparity maps calculation. Microprocessors and Microsystems - Embedded Hardware Design 36(4): 281-288 (2012)
	2011
45		Fabio Frustaci, Pasquale Corsonello, Massimo Alioto: Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers. ECCTD 2011: 592-595
44		Fabio Frustaci, Pasquale Corsonello, Massimo Alioto: Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology. ISCAS 2011: 2075-2078
43		Fabio Frustaci, Massimo Alioto, Pasquale Corsonello: Tapered-Vth Approach for Energy-Efficient CMOS Buffers. IEEE Trans. on Circuits and Systems 58-I(11): 2698-2707 (2011)
42		Luca Magnelli, Felice Crupi, Pasquale Corsonello, Calogero Pace, Giuseppe Iannaccone: A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference. J. Solid-State Circuits 46(2): 465-474 (2011)
	2010
41		Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello: A new low-power high-speed single-clock-cycle binary comparator. ISCAS 2010: 317-320
40		Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello: Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. ISVLSI 2010: 458-459
39		Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello: Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. PATMOS 2010: 180-189
38		Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello: Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. TRETS 4(1): 8 (2010)
	2009
37		Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello: New performance/power/area efficient, reliable full adder design. ACM Great Lakes Symposium on VLSI 2009: 493-498
36		Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello: An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. ARC 2009: 74-84
35		Aakash Jain, Giovanni Staino, Pasquale Corsonello: Quad-Port Memory Blocks in Radiation-Tolerant FPGAs: An Application for Image Processing Systems. ICETET 2009: 368-371
34		Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala: Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design 2009: 45-50
33		Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello: Designing High-Speed Adders in Power-Constrained Environments. IEEE Trans. on Circuits and Systems 56-II(2): 172-176 (2009)
32		Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala: Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. J. Low Power Electronics 5(3): 326-338 (2009)
	2008
31		Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo: A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. PATMOS 2008: 277-286
30		Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala: Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. PATMOS 2008: 297-306
29		Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello: Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. ReConFig 2008: 217-222
28		Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello: Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. SoCC 2008: 375-378
27		Stefania Perri, Pasquale Corsonello: Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator. IEEE Trans. on Circuits and Systems 55-II(12): 1239-1243 (2008)
26		Paolo Zicari, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo: A matrix product accelerator for field programmable systems on chip. Microprocessors and Microsystems - Embedded Hardware Design 32(2): 53-67 (2008)
25		Paolo Zicari, Emanuele Sciagura, Stefania Perri, Pasquale Corsonello: A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals. Microprocessors and Microsystems - Embedded Hardware Design 32(8): 437-446 (2008)
	2007
24		Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala: A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. AHS 2007: 119-126
23		Emanuele Sciagura, Paolo Zicari, Stefania Perri, Pasquale Corsonello: An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector. DSD 2007: 102-108
22		Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo: Design and Implementation of a 90nm Low bit-rate Image Compression Core. DSD 2007: 383-389
21		Marco Lanuzza, Stefania Perri, Pasquale Corsonello: MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. SAMOS 2007: 159-168
	2006
20		Pasquale Corsonello, Stefania Perri, Martin Margala: An integrated countermeasure against differential power analysis for secure smart-cards. ISCAS 2006
19		Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo: Leakage energy reduction techniques in deep submicron cache memories: a comparative study. ISCAS 2006
18		Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo: Low bit rate image compression core for onboard space applications. IEEE Trans. Circuits Syst. Video Techn. 16(1): 114-128 (2006)
17		Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo: Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. IEEE Trans. VLSI Syst. 14(11): 1238-1249 (2006)
16		Stefania Perri, Maria Antonia Iachino, Pasquale Corsonello: Simd Multipliers for Accelerating Embedded Processors in FPGAS. Journal of Circuits, Systems, and Computers 15(4): 537-550 (2006)
	2005
15		Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello: Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. FPL 2005: 13-18
14		Marco Lanuzza, Martin Margala, Pasquale Corsonello: Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. ISLPED 2005: 161-166
13		Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo: Fast Low-Power 64-Bit Modular Hybrid Adder. PATMOS 2005: 609-617
12		Pasquale Corsonello, Stefania Perri: Efficient Reconfigurable Manchester Adders for Low-power Media Processing. Journal of Circuits, Systems, and Computers 14(1): 57-64 (2005)
11		Pasquale Corsonello, Stefania Perri, Paolo Zicari, Giuseppe Cocorullo: Microprocessor-based FPGA implementation of SPIHT image compression subsystems. Microprocessors and Microsystems 29(6): 299-305 (2005)
10		Stefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo: A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocessors and Microsystems 29(8-9): 381-391 (2005)
	2004
9		Pasquale Corsonello, Stefania Perri, Vitit Kantabutra: Area- and Power-Reduced Standard-Cell Spanning Tree Adders. ESA/VLSI 2004: 343-352
8		Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo: Variable precision arithmetic circuits for FPGA-based multimedia processors. IEEE Trans. VLSI Syst. 12(9): 995-999 (2004)
	2003
7		Pasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe Cocorullo: Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems. FPL 2003: 661-669
6		Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo: A high-speed energy-efficient 64-bit reconfigurable binary adder. IEEE Trans. VLSI Syst. 11(5): 939-943 (2003)
	2002
5		Pasquale Corsonello, Giandomenico Spezzano, Giovanni Staino, Domenico Talia: Efficient Implementation of Cellular Algorithms on Reconfigurable Hardware. PDP 2002: 211-218
4		Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo: VLSI circuits for low-power high-speed asynchronous addition. IEEE Trans. VLSI Syst. 10(5): 608-613 (2002)
	2000
3		Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo: Designing High-Speed Asynchronous Pipelines. EUROMICRO 2000: 1394-1399
2		Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo: VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. PATMOS 2000: 195-204
1		Pasquale Corsonello, Stefania Perri, G. Cororullo: Area-time-power tradeoff in cellular arrays VLSI implementations. IEEE Trans. VLSI Syst. 8(5): 614-624 (2000)

Coauthor Index

1	Massimo Alioto	[43] [44] [45]
2	Sai Rahul Chalamalasetti	[28] [29]
3	Giuseppe Cocorullo	[2] [3] [4] [6] [7] [8] [10] [11] [13] [17] [18] [19] [22] [26] [31] [46]
4	G. Cororullo	[1]
5	Felice Crupi	[42]
6	Fabio Frustaci	[17] [19] [31] [33] [36] [38] [39] [40] [41] [43] [44] [45] [47]
7	Maria Antonia Iachino	[7] [8] [16]
8	Giuseppe Iannaccone	[42]
9	Aakash Jain	[35]
10	Vitit Kantabutra	[9]
11	Marco Lanuzza	[8] [10] [14] [15] [18] [21] [22] [24] [30] [32] [33] [34] [36] [37] [38] [39] [40] [41]
12	Luca Magnelli	[42]
13	Martin Margala	[14] [15] [20] [24] [28] [29] [30] [32] [34] [37]
14	Calogero Pace	[42]
15	Stefania Perri	[1] [2] [3] [4] [6] [7] [8] [9] [10] [11] [12] [13] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [30] [31] [32] [33] [34] [36] [38] [39] [40] [41] [46] [47]
16	Sohan Purohit	[28] [29] [32] [34] [37]
17	Raffaele De Rose	[39] [40]
18	Emanuele Sciagura	[23] [25]
19	Giandomenico Spezzano	[5]
20	Giovanni Staino	[5] [18] [22] [35]
21	Domenico Talia	[5]
22	Paolo Zicari	[11] [23] [25] [26] [33] [36] [38] [46]

Last update Tue May 29 20:41:18 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page