 | 2011 |
| 13 |  | Xiaohui Zhang,
Ming Cong,
Guangqiang Chen:
Software and Hardware Co-designed Multi-level TLBs for Chip Multiprocessors.
CIT 2011: 609-614 |
| 12 |  | Xiaohui Zhang,
Yifei Jiang,
Ming Cong:
Performance Improvement for Multicore Processors Using Variable Page Technologies.
NAS 2011: 230-235 |
| 2010 |
| 11 |  | Ming Cong,
Zhanbo Chang,
Yu Du,
Weiliang Xu:
Modeling and simulation of masticatory robot.
Humanoids 2010: 198-203 |
| 10 |  | Yongqing Ren,
Hong An,
Tao Sun,
Ming Cong,
Yaobin Wang:
Dynamic Resource Tuning for Flexible Core Chip Multiprocessors.
ICA3PP (2) 2010: 32-41 |
| 9 |  | Ming Cong,
Hong An,
Lu Cao,
Yuan Liu,
Peng Li,
Tao Wang,
Zhihong Yu,
Dong Liu:
Pattern-Unit Based Regular Expression Matching with Reconfigurable Function Unit.
ICCSA (4) 2010: 427-440 |
| 8 |  | Liang Yang,
Bao-Xia Fan,
Ming Cong,
Ji-Ye Zhao:
Register relocation to optimize clock network for multi-domain clock skew scheduling.
ISCAS 2010: 3180-3183 |
| 7 |  | Ming Cong,
Huili Shi:
A study of magnetic fluid rotary seals for wafer handling robot.
IJISTA 8(1/2/3/4): 158-170 (2010) |
| 6 |  | Ming Cong,
Xiaofei Xu,
Peter Xu:
Time-jerk synthetic optimal trajectory planning of robot based on fuzzy genetic algorithm.
IJISTA 8(1/2/3/4): 185-199 (2010) |
| 5 |  | Ming Cong,
Teng Li:
Design and application of magnetic coupling used for ultra-high vacuum robot.
IJISTA 8(1/2/3/4): 231-246 (2010) |
| 2009 |
| 4 |  | Yongqing Ren,
Hong An,
Ming Cong,
Guang Xu,
Li Wang:
Scaling the Performance of Tiled Processor Architectures with On-Chip-Network Topology.
CSO (1) 2009: 77-81 |
| 3 |  | Ming Cong,
Penglei Dai,
Huili Shi:
A Study on Wafer-Handling Robot with Coaxial Twin-Shaft Magnetic Fluid Seals.
ICIRA 2009: 1123-1137 |
| 2008 |
| 2 |  | Ming Cong,
Jing Liu,
Quanpu Li:
A Novel Dual-Cam Linkage Drive Automatic Tool Changer for Horizontal Machining Center.
ICIRA (2) 2008: 368-377 |
| 2007 |
| 1 |  | Yaobin Wang,
Hong An,
Bo Liang,
Li Wang,
Ming Cong,
Yongqing Ren:
Balancing Thread Partition for Efficiently Exploiting Speculative Thread-Level Parallelism.
APPT 2007: 40-49 |