José Manuel Colmenar

	2010
13		José Luis Risco-Martín, José Manuel Colmenar, David Atienza, José Ignacio Hidalgo: Simulation of High-Performance Memory Allocators. DSD 2010: 275-282
12		José Manuel Colmenar, José L. Risco-Martín, David Atienza, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares: Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution. GECCO 2010: 1227-1234
11		José L. Risco-Martín, David Atienza, José Manuel Colmenar, Oscar Garnica: A parallel evolutionary algorithm to optimize dynamic memory managers in embedded systems. Parallel Computing 36(10-11): 572-590 (2010)
	2009
10		José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo: Characterizing asynchronous variable latencies through probability distribution functions. Microprocessors and Microsystems - Embedded Hardware Design 33(7-8): 483-497 (2009)
	2008
9		José Manuel Colmenar, Noelia Morón, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo: Modelling Asynchronous Systems using Probability Distribution Functions. PDP 2008: 3-11
	2007
8		Guadalupe Miñana, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar, Oscar Garnica, Sonia López: Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders. IET Computers & Digital Techniques 1(2): 113-119 (2007)
	2006
7		José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López: Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. DSD 2006: 423-432
6		Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar: A Power-Aware Technique for Functional Units in High-Performance Processors. DSD 2006: 456-459
5		José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López: Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. Euro-Par 2006: 495-505
4		Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López: A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. PATMOS 2006: 514-523
	2005
3		Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar: Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. PATMOS 2005: 40-48
	2004
2		Sonia López, Oscar Garnica, José Manuel Colmenar: Enhancing GALS Processor Performance Using Data Classification Based on Data Latency. PATMOS 2004: 623-632
1		José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida: Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. PDP 2004: 112-119

Coauthor Index

1	David Atienza (David Atienza Alonso)	[11] [12] [13]
2	Oscar Garnica	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
3	Román Hermida	[1]
4	José Ignacio Hidalgo	[1] [3] [4] [5] [6] [7] [8] [9] [10] [12] [13]
5	Juan Lanchares	[1] [3] [4] [5] [6] [7] [8] [9] [10] [12]
6	Sonia López	[1] [2] [4] [5] [7] [8]
7	Guadalupe Miñana	[3] [4] [5] [6] [7] [8]
8	Noelia Morón	[9]
9	José Luis Risco-Martín (José L. Risco-Martín)	[11] [12] [13]

Last update Tue May 29 01:28:40 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page