Jovanka Ciric

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2003

3 Jovanka Ciric, Carl Sechen: Efficient canonical form for Boolean matching of complex functions in large libraries. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 535-544 (2003)

2001

2 Jovanka Ciric, Carl Sechen: Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries. ICCAD 2001: 610-617

2000

1 Jovanka Ciric, Gin Yee, Carl Sechen: Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. DATE 2000: 277-282

	2003
3		Jovanka Ciric, Carl Sechen: Efficient canonical form for Boolean matching of complex functions in large libraries. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 535-544 (2003)
	2001
2		Jovanka Ciric, Carl Sechen: Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries. ICCAD 2001: 610-617
	2000
1		Jovanka Ciric, Gin Yee, Carl Sechen: Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. DATE 2000: 277-282

Coauthor Index

1 Carl Sechen [1] [2] [3]

2 Gin Yee [1]

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