Maciej J. Ciesielski

	2011
53		Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang: Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. DATE 2011: 1584-1589
52		Dusung Kim, Maciej J. Ciesielski, Seiyang Yang: A new distributed event-driven gate-level HDL simulation by accurate prediction. DATE 2011: 547-550
51		S. Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski: Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. VLSI Design 2011: 304-309
50		Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski: A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. J. Low Power Electronics 7(4): 471-481 (2011)
	2010
49		Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon: Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams. HLDVT 2010: 33-39
	2009
48		Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon: Optimizing data flow graphs to minimize hardware implementation. DATE 2009: 117-122
47		Maciej J. Ciesielski, Jérémie Guillot, Daniel Gomez-Prado, Emmanuel Boutillon: High-Level Dataflow Transformations Using Taylor Expansion Diagrams. IEEE Design & Test of Computers 26(4): 46-57 (2009)
46		Maciej J. Ciesielski, Daniel Gomez-Prado, Q. Ren, Jérémie Guillot, Emmanuel Boutillon: Optimization of Data-Flow Computations Using Canonical TED Representation. IEEE Trans. on CAD of Integrated Circuits and Systems 28(9): 1321-1333 (2009)
	2008
45		Kyuho Shim, Youngrae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang: A fast two-pass HDL simulation with on-demand dump. ASP-DAC 2008: 422-427
44		Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang: Simulation Acceleration with HW Re-Compilation Avoidance. VLSI Design 2008: 487-491
	2007
43		Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon: Data-flow transformations using Taylor expansion diagrams. DATE 2007: 455-460
	2006
42		Jérémie Guillot, Emmanuel Boutillon, Q. Ren, Maciej J. Ciesielski, Daniel Gomez-Prado, Serkan Askar: Efficient factorization of DSP transforms using taylor expansion diagrams. DATE 2006: 754-755
41		Maciej J. Ciesielski, Priyank Kalla, Serkan Askar: Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. IEEE Trans. Computers 55(9): 1188-1201 (2006)
	2005
40		Zhaojun Wo, Israel Koren, Maciej J. Ciesielski: An ILP Formulation for Yield-driven Architectural Synthesis. DFT 2005: 12-20
39		Zhaojun Wo, Israel Koren, Maciej J. Ciesielski: Yield-aware Floorplanning. DSD 2005: 247-253
38		Zhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski: Functional test generation based on word-level SAT. Journal of Systems Architecture 51(8): 488-511 (2005)
	2004
37		Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski: A new state assignment technique for testing and low power. DAC 2004: 510-513
36		Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski: Algorithms for Taylor Expansion Diagrams. ISMVL 2004: 235-240
	2003
35		Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski: Fast Computation of Data Correlation Using BDDs. DATE 2003: 10122-10129
	2002
34		Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre: Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE 2002: 285-289
33		Maciej J. Ciesielski, Serkan Askar, Samuel Levitin: Analytical approach to layout generation of datapath cells. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1480-1488 (2002)
32		Priyank Kalla, Maciej J. Ciesielski: A comprehensive approach to the partial scan problem using implicitstate enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 810-826 (2002)
31		Congguang Yang, Maciej J. Ciesielski: BDS: a BDD-based logic optimization system. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 866-876 (2002)
	2001
30		Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski: LPSAT: a unified approach to RTL satisfiability. DATE 2001: 398-402
29		Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre: Functional Test Generation using Constraint Logic Programming. VLSI-SOC 2001: 375-387
28		Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski: Strategies for solving the Boolean satisfiability problem using binary decision diagrams. Journal of Systems Architecture 47(6): 491-503 (2001)
	2000
27		Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal: BDS: a BDD-based logic optimization system. DAC 2000: 92-97
26		Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang: A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. DATE 2000: 232-236
25		Congguang Yang, Maciej J. Ciesielski: Synthesis for Mixed CMOS/PTl Logic. DATE 2000: 750
24		Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski: Retiming-based factorization for sequential logic optimization. ACM Trans. Design Autom. Electr. Syst. 5(3): 373-398 (2000)
	1999
23		Priyank Kalla, Maciej J. Ciesielski: Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. DATE 1999: 638-642
22		Serkan Askar, Maciej J. Ciesielski: Analytical approach to custom datapath design. ICCAD 1999: 98-101
21		Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal: BDD Decomposition for Efficient Logic Synthesis. ICCD 1999: 626-
20		Durgam Vahia, Maciej J. Ciesielski: Transistor level placement for full custom datapath cell design. ISPD 1999: 158-163
	1998
19		Balakrishnan Iyer, Maciej J. Ciesielski: Reencoding for cycle-time minimization under fixed encoding length. ICCAD 1998: 312-315
18		Priyank Kalla, Maciej J. Ciesielski: A comprehensive approach to the partial scan problem using implicit state enumeration. ITC 1998: 651-657
17		Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu: Wave-pipelining: a tutorial and research survey. IEEE Trans. VLSI Syst. 6(3): 464-474 (1998)
	1997
16		Imrich Chlamtac, Maciej J. Ciesielski, Andrea Fumagalli, Chester A. Ruszczyk, Gosse Wedzinga: Intelligent Simulation for Computer Aided Design of Optical Networks. ONDM 1997: 73-86
15		Priyank Kalla, Maciej J. Ciesielski: Testability of Sequential Circuits with Multi-Cycle False Path. VTS 1997: 322-328
	1996
14		Balakrishnan Iyer, Maciej J. Ciesielski: Metamorphosis: state assignment by retiming and re-encoding. ICCAD 1996: 614-617
	1994
13		Wayne Burleson, L. W. Cotten, Fabian Klass, Maciej J. Ciesielski: Forum: Wave-pipelining: Is it Practical? ISCAS 1994: 163-166
	1993
12		Donald A. Joy, Maciej J. Ciesielski: Clock period minimization with wave pipelining. IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 461-472 (1993)
	1992
11		Maya K. Yajnik, Maciej J. Ciesielski: Finite State Machine Decomposition Using Multiway Partitioning. ICCD 1992: 320-323
10		Zafar Hasan, David Harrison, Maciej J. Ciesielski: A Fast Partitioning Method for PLA-Based FPGAs. IEEE Design & Test of Computers 9(4): 34-39 (1992)
9		Maciej J. Ciesielski, Seiyang Yang: PLADE: a two-stage PLA decomposition. IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 943-954 (1992)
	1991
8		Maciej J. Ciesielski, Jia-Jye Shen, Marc Davio: A Unified Approach to Input-Output Encoding for FSM State Assignment. DAC 1991: 176-181
7		Donald A. Joy, Maciej J. Ciesielski: Placement for Clock Period Minimization With Multiple Wave Propagation. DAC 1991: 640-643
6		Seiyang Yang, Maciej J. Ciesielski: Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 4-12 (1991)
	1989
5		Maciej J. Ciesielski: Layer assignment for VLSI interconnect delay minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 702-707 (1989)
	1987
4		Maciej J. Ciesielski, Edwin Kinnen: Digraph Relaxation for 2-Dimensional Placement of IC Blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 6(1): 55-66 (1987)
	1985
3		Maciej J. Ciesielski: Two-Dimensional Routing for the Silc Silicon Compiler. IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 198-203 (1985)
	1982
2		Maciej J. Ciesielski, Edwin Kinnen: An analytical method for compacting routing area in integrated circuits. DAC 1982: 30-37
	1981
1		Maciej J. Ciesielski, Edwin Kinnen: An optimum layer assignment for routing in ICs and PCBs. DAC 1981: 733-737

Coauthor Index

1	Serkan Askar	[22] [33] [41] [42] [43]
2	Hyuncheol Baik	[45]
3	S. Banerjee	[51]
4	Shibaji Banerjee	[50]
5	Surendra Bommu	[24]
6	Emmanuel Boutillon	[42] [43] [46] [47] [48] [49]
7	Wayne P. Burleson (Wayne Burleson)	[13] [17]
8	Imrich Chlamtac	[16]
9	Sangwook Cho	[37]
10	Youngrae Cho	[45]
11	Kyumyung Choi	[45]
12	L. W. Cotten	[13]
13	Marc Davio	[8]
14	Rolf Drechsler	[36]
15	Görschwin Fey	[36]
16	Andrea Fumagalli	[16]
17	Daniel Gomez-Prado	[42] [43] [46] [47] [48] [49]
18	Jérémie Guillot	[42] [43] [46] [47] [48]
19	Ian G. Harris	[35]
20	David Harrison	[10]
21	Zafar Hasan	[10]
22	ChiLai Huang	[26]
23	Balakrishnan Iyer	[14] [19]
24	Donald A. Joy	[7] [12]
25	Priyank Kalla	[15] [18] [23] [26] [28] [30] [32] [34] [41]
26	Dusung Kim	[45] [49] [52] [53]
27	Jaebum Kim	[45]
28	Kyungkuk Kim	[45]
29	Namdo Kim	[45]
30	Edwin Kinnen	[1] [2] [4]
31	Fabian Klass	[13] [17]
32	Israel Koren	[39] [40]
33	Samuel Levitin	[33]
34	W. Liu	[17]
35	Jimson Mathew	[50] [51]
36	Byeongun Min	[45]
37	Saraju P. Mohanty	[50] [51]
38	Niall O'Neill	[24]
39	Sungju Park	[37]
40	Dhiraj K. Pradhan	[50] [51]
41	Q. Ren	[42] [46] [48]
42	Bruno Rouzeyre	[29] [34]
43	Chester A. Ruszczyk	[16]
44	Jia-Jye Shen	[8]
45	Kyuho Shim	[44] [45] [53]
46	Vigyan Singhal	[21] [27]
47	Kesava R. Talupuru	[38] [44]
48	Durgam Vahia	[20]
49	Gosse Wedzinga	[16]
50	Zhaojun Wo	[39] [40]
51	Maya K. Yajnik	[11]
52	Congguang Yang	[21] [25] [27] [31]
53	Seiyang Yang	[6] [9] [37] [44] [45] [52] [53]
54	Zhihong Zeng	[26] [28] [29] [30] [34] [35] [38]
55	Qiushuang Zhang	[35]

Colors in the list of coauthors

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