 | 2012 |
| 16 |  | Jaeyong Chung,
Jacob A. Abraham:
Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA.
IEEE Trans. on CAD of Integrated Circuits and Systems 31(4): 485-496 (2012) |
| 15 |  | Jaeyong Chung,
Jinjun Xiong,
Vladimir Zolotov,
Jacob A. Abraham:
Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator.
IEEE Trans. on CAD of Integrated Circuits and Systems 31(4): 497-508 (2012) |
| 2011 |
| 14 |  | Jaeyong Chung,
Jinjun Xiong,
Vladimir Zolotov,
Jacob A. Abraham:
Path criticality computation in parameterized statistical timing analysis.
ASP-DAC 2011: 249-254 |
| 13 |  | Eun Jung Jang,
Jaeyong Chung,
Anne E. Gattiker,
Sani R. Nassif,
Jacob A. Abraham:
Post-Silicon Timing Validation Method Using Path Delay Measurements.
Asian Test Symposium 2011: 232-237 |
| 12 |  | Jaeyong Chung,
Jinjun Xiong,
Vladimir Zolotov,
Jacob A. Abraham:
Testability driven statistical path selection.
DAC 2011: 417-422 |
| 11 |  | Kihyuk Han,
Joonsung Park,
Jae Wook Lee,
Jaeyong Chung,
Eonjo Byun,
Cheol-Jong Woo,
Sejang Oh,
Jacob A. Abraham:
Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip.
J. Electronic Testing 27(4): 429-439 (2011) |
| 2010 |
| 10 |  | Joonsung Park,
Jae Wook Lee,
Jaeyong Chung,
Kihyuk Han,
Jacob A. Abraham,
Eonjo Byun,
Cheol-Jong Woo,
Sejang Oh:
At-speed Test of High-Speed DUT Using Built-Off Test Interface.
Asian Test Symposium 2010: 269-274 |
| 9 |  | Hyunjin Kim,
Jaeyong Chung,
Jacob A. Abraham,
Eonjo Byun,
Cheol-Jong Woo:
A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control.
European Test Symposium 2010: 145-150 |
| 8 |  | Jaeyong Chung,
Joonsung Park,
Jacob A. Abraham,
Eonjo Byun,
Cheol-Jong Woo:
Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate.
VTS 2010: 33-38 |
| 2009 |
| 7 |  | Joonsung Park,
Jaeyong Chung,
Jacob A. Abraham:
LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits.
Asian Test Symposium 2009: 373-378 |
| 6 |  | Jaeyong Chung,
Jacob A. Abraham:
A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA.
ICCAD 2009: 321-327 |
| 5 |  | Jaeyong Chung,
Henry J. Gardner:
Measuring temporal variation in presence during game playing.
VRCAI 2009: 163-168 |
| 4 |  | Jaeyong Chung,
Jacob A. Abraham:
Recursive Path Selection for Delay Fault Testing.
VTS 2009: 65-70 |
| 2006 |
| 3 |  | Jungyoul Lim,
Jaeyong Chung,
Jinryong Kim,
Kwanghyun Shim:
A Dynamic Load Balancing for Massive Multiplayer Online Game Server.
ICEC 2006: 239-249 |
| 2004 |
| 2 |  | YungWoo Jung,
Bum-Hyun Lim,
Kwang-Hyun Sim,
Hunjoo Lee,
Ilkyu Park,
Jaeyong Chung,
Jihong Lee:
VENUS: The Online Game Simulator Using Massively Virtual Clients.
AsiaSim 2004: 589-596 |
| 2003 |
| 1 |  | Jaeyong Chung,
Gwanghyun Shim,
Byungtae Choi:
Driving Virtual Human using the Hybrid of Position-based and Angle-based Control Mode.
Modelling, Simulation, and Optimization 2003: 194-199 |