B. Chung

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2008

3 B. Chung, J. B. Kuo: Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application. Integration 41(1): 9-16 (2008)

2006

2 B. Chung, J. B. Kuo: Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology. ISCAS 2006

1 B. Chung, J. B. Kuo: Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique. PATMOS 2006: 237-246

	2008
3		B. Chung, J. B. Kuo: Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application. Integration 41(1): 9-16 (2008)
	2006
2		B. Chung, J. B. Kuo: Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology. ISCAS 2006
1		B. Chung, J. B. Kuo: Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique. PATMOS 2006: 237-246

Coauthor Index

1 J. B. Kuo [1] [2] [3]

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