Jong Ching Chuen

List of publications from the DBLP Bibliography Server - FAQ

Ask others: ACM DL/Guide -

- CSB - MetaPress - Google - Bing - Yahoo

2006

3 Luo Jianwen, Jong Ching Chuen: Matrix Inversion on Reconfigurable Hardware using Binary-coded z-path CORDIC. APCCAS 2006: 1176-1179

2004

2 Luo Jianwen, Jong Ching Chuen: Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs. DSD 2004: 244-248

2002

1 Zhaoxuan Shen, Jong Ching Chuen: Lower Bound Estimation of Hardware Resources for Scheduling in High-Level Synthesis. J. Comput. Sci. Technol. 17(6): 718-730 (2002)

	2006
3		Luo Jianwen, Jong Ching Chuen: Matrix Inversion on Reconfigurable Hardware using Binary-coded z-path CORDIC. APCCAS 2006: 1176-1179
	2004
2		Luo Jianwen, Jong Ching Chuen: Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs. DSD 2004: 244-248
	2002
1		Zhaoxuan Shen, Jong Ching Chuen: Lower Bound Estimation of Hardware Resources for Scheduling in High-Level Synthesis. J. Comput. Sci. Technol. 17(6): 718-730 (2002)

Coauthor Index

1 Luo Jianwen [2] [3]

2 Zhaoxuan Shen [1]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team —

Data released under the ODC-BY 1.0 license — See also our legal information page