 | 2012 |
| 11 |  | Da-Cheng Juan,
Yi-Lin Chuang,
Diana Marculescu,
Yao-Wen Chang:
Statistical thermal modeling and optimization considering leakage power variations.
DATE 2012: 605-610 |
| 2011 |
| 10 |  | Yi-Lin Chuang,
Hong-Ting Lin,
Tsung-Yi Ho,
Yao-Wen Chang,
Diana Marculescu:
PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs.
ICCAD 2011: 85-90 |
| 9 |  | Hong-Ting Lin,
Yi-Lin Chuang,
Tsung-Yi Ho:
Pulsed-latch-based clock tree migration for dynamic power reduction.
ISLPED 2011: 39-44 |
| 8 |  | Yi-Lin Chuang,
Po-Wei Lee,
Yao-Wen Chang:
Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1649-1662 (2011) |
| 7 |  | Yi-Lin Chuang,
Sangmin Kim,
Youngsoo Shin,
Yao-Wen Chang:
Pulsed-Latch Aware Placement for Timing-Integrity Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 30(12): 1856-1869 (2011) |
| 2010 |
| 6 |  | Yi-Lin Chuang,
Sangmin Kim,
Youngsoo Shin,
Yao-Wen Chang:
Pulsed-latch aware placement for timing-integrity optimization.
DAC 2010: 280-285 |
| 5 |  | Yi-Lin Chuang,
Gi-Joon Nam,
Charles J. Alpert,
Yao-Wen Chang,
Jarrod A. Roy,
Natarajan Viswanathan:
Design-hierarchy aware mixed-size placement for routability optimization.
ICCAD 2010: 663-668 |
| 2009 |
| 4 |  | Yi-Lin Chuang,
Po-Wei Lee,
Yao-Wen Chang:
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs.
ICCAD 2009: 666-673 |
| 2008 |
| 3 |  | Hsin-Chen Chen,
Yi-Lin Chuang,
Yao-Wen Chang,
Yung-Chung Chang:
Constraint graph-based macro placement for modern mixed-size circuit designs.
ICCAD 2008: 218-223 |
| 2 |  | Tung-Chieh Chen,
Yi-Lin Chuang,
Yao-Wen Chang:
Effective Wire Models for X-Architecture Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 654-658 (2008) |
| 2007 |
| 1 |  | Tung-Chieh Chen,
Yi-Lin Chuang,
Yao-Wen Chang:
X-architecture placement based on effective wire models.
ISPD 2007: 87-94 |