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Yi-Lin Chuang Coauthor index pubzone.org

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DBLP keys2012
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDa-Cheng Juan, Yi-Lin Chuang, Diana Marculescu, Yao-Wen Chang: Statistical thermal modeling and optimization considering leakage power variations. DATE 2012: 605-610
2011
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu: PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. ICCAD 2011: 85-90
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho: Pulsed-latch-based clock tree migration for dynamic power reduction. ISLPED 2011: 39-44
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang: Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1649-1662 (2011)
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang: Pulsed-Latch Aware Placement for Timing-Integrity Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 30(12): 1856-1869 (2011)
2010
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang: Pulsed-latch aware placement for timing-integrity optimization. DAC 2010: 280-285
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan: Design-hierarchy aware mixed-size placement for routability optimization. ICCAD 2010: 663-668
2009
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang: Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. ICCAD 2009: 666-673
2008
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang: Constraint graph-based macro placement for modern mixed-size circuit designs. ICCAD 2008: 218-223
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang: Effective Wire Models for X-Architecture Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 654-658 (2008)
2007
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang: X-architecture placement based on effective wire models. ISPD 2007: 87-94

Coauthor Index

1Charles J. Alpert [5]
2Yao-Wen Chang [1] [2] [3] [4] [5] [6] [7] [8] [10] [11]
3Yung-Chung Chang [3]
4Hsin-Chen Chen [3]
5Tung-Chieh Chen [1] [2]
6Tsung-Yi Ho [9] [10]
7Da-Cheng Juan [11]
8Sangmin Kim [6] [7]
9Po-Wei Lee [4] [8]
10Hong-Ting Lin [9] [10]
11Diana Marculescu [10] [11]
12Gi-Joon Nam [5]
13Jarrod A. Roy [5]
14Youngsoo Shin [6] [7]
15Natarajan Viswanathan [5]

Last update Sun May 27 04:04:01 2012 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page