Chris C. N. Chu

Chris Chu, Chris Chong-Nuen Chu

	2012
82		Jackey Z. Yan, Chris Chu: Optimal slack-driven block shaping algorithm in fixed-outline floorplanning. ISPD 2012: 179-186
	2011
81		Yue Xu, Chris Chu: MGR: Multi-level global router. ICCAD 2011: 250-255
80		Yanheng Zhang, Chris Chu: RegularRoute: an efficient detailed router with regular routing patterns. ISPD 2011: 45-52
79		Gaurav Ajwani, Chris Chu, Wai-Kei Mak: FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 194-204 (2011)
78		Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak: SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 30(7): 1020-1033 (2011)
	2010
77		Yue Xu, Chris Chu: An auction based pre-processing technique to determine detour in global routing. ICCAD 2010: 305-311
76		Yue Xu, Chris Chu: A matching based decomposer for double patterning lithography. ISPD 2010: 121-126
75		Jackey Z. Yan, Chris Chu, Wai-Kei Mak: SafeChoice: a novel clustering algorithm for wirelength-driven placement. ISPD 2010: 185-192
74		Gaurav Ajwani, Chris Chu, Wai-Kei Mak: FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. ISPD 2010: 27-34
73		Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu: ITOP: integrating timing optimization within placement. ISPD 2010: 83-90
72		Jackey Z. Yan, Chris Chu: DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 367-381 (2010)
	2009
71		Yue Xu, Yanheng Zhang, Chris Chu: FastRoute 4.0: global router with efficient via minimization. ASP-DAC 2009: 576-581
70		Jackey Z. Yan, Natarajan Viswanathan, Chris Chu: Handling complexities in modern large-scale mixed-size placement. DAC 2009: 436-441
69		Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang: Pad assignment for die-stacking System-in-Package design. ICCAD 2009: 249-255
68		Yanheng Zhang, Chris Chu: CROP: Fast and effective congestion refinement of placement. ICCAD 2009: 344-350
67		Yue Xu, Chris Chu: GREMA: Graph reduction based efficient mask assignment for double patterning technology. ICCAD 2009: 601-606
66		Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu: Handling routability in floorplan design with twin binary trees. Integration 42(4): 449-456 (2009)
	2008
65		Jackey Z. Yan, Chris Chu: DeFer: deferred decision making enabled fixed-outline floorplanner. DAC 2008: 161-166
64		Yanheng Zhang, Yue Xu, Chris Chu: FastRoute3.0: a fast and high quality global router based on virtual capacity. ICCAD 2008: 344-349
63		Chris Chu: Wire Sizing. Encyclopedia of Algorithms 2008
62		Chris C. N. Chu, Yiu-Chung Wong: FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 70-83 (2008)
	2007
61		Natarajan Viswanathan, Min Pan, Chris C. N. Chu: FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. ASP-DAC 2007: 135-140
60		Min Pan, Chris C. N. Chu, Priyadarshan Patra: A Novel Performance-Driven Topology Design Algorithm. ASP-DAC 2007: 244-249
59		Min Pan, Chris C. N. Chu: FastRoute 2.0: A High-quality and Efficient Global Router. ASP-DAC 2007: 250-255
58		Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu: RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC 2007: 453-458
57		Min Pan, Chris C. N. Chu: IPR: An Integrated Placement and Routing Algorithm. DAC 2007: 59-62
56		Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia: The coming of age of physical synthesis. ICCAD 2007: 246-249
55		Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu: Wire Retiming Problem With Net Topology Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1648-1660 (2007)
	2006
54		Natarajan Viswanathan, Min Pan, Chris C. N. Chu: FastPlace 2.0: an efficient analytical placer for mixed-mode designs. ASP-DAC 2006: 195-200
53		Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu: Optimal cell flipping in placement and floorplanning. DAC 2006: 1109-1114
52		Chuan Lin, Hai Zhou, Chris C. N. Chu: A revisit to floorplan optimization by Lagrangian relaxation. ICCAD 2006: 164-171
51		Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu: Analog placement with symmetry and other placement constraints. ICCAD 2006: 349-354
50		Min Pan, Chris C. N. Chu: FastRoute: a step to integrate global routing into placement. ICCAD 2006: 464-471
49		Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu: Post-placement voltage island generation. ICCAD 2006: 641-646
	2005
48		Min Pan, Natarajan Viswanathan, Chris C. N. Chu: An efficient and effective detailed placement algorithm. ICCAD 2005: 48-55
47		Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li: Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages. ICCD 2005: 38-44
46		Min Pan, Chris C. N. Chu, J. Morris Chang: Transition time bounded low-power clock tree construction. ISCAS (3) 2005: 2445-2448
45		Min Pan, Chris C. N. Chu, Hai Zhou: Timing yield estimation using statistical static timing analysis. ISCAS (3) 2005: 2461-2464
44		Natarajan Viswanathan, Min Pan, Chris C. N. Chu: FastPlace: an analytical placer for mixed-mode designs. ISPD 2005: 221-223
43		Chris C. N. Chu, Yiu-Chung Wong: Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. ISPD 2005: 28-35
42		Sampath Dechu, Zion Cien Shen, Chris C. N. Chu: An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 600-608 (2005)
41		Natarajan Viswanathan, Chris C. N. Chu: FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 722-733 (2005)
	2004
40		Sampath Dechu, Zion Cien Shen, Chris C. N. Chu: An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations. ASP-DAC 2004: 361-366
39		Zion Cien Shen, Chris C. N. Chu: Accurate and efficient flow based congestion estimation in floorplanning. ASP-DAC 2004: 671-676
38		Chris Chu: FLUTE: fast lookup table based wirelength estimation technique. ICCAD 2004: 696-701
37		Debjit Sinha, Hai Zhou, Chris C. N. Chu: Optimal gate sizing for coupling-noise reduction. ISPD 2004: 176-181
36		Natarajan Viswanathan, Chris C. N. Chu: FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. ISPD 2004: 26-33
35		Arif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu: Fitted Elmore delay: a simple and accurate interconnect delay model. IEEE Trans. VLSI Syst. 12(7): 691-696 (2004)
34		Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho: Placement constraints in floorplan design. IEEE Trans. VLSI Syst. 12(7): 735-745 (2004)
33		Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 136-141 (2004)
32		Chris C. N. Chu, Evangeline F. Y. Young: Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 71-79 (2004)
	2003
31		Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu: A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. DATE 2003: 10856-10861
30		Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu: Retiming with Interconnect and Gate Delay. ICCAD 2003: 221-226
29		Wei Zou, Chris Chu, Sudhakar M. Reddy, Irith Pomeranz: Optimizing SOC Test Resources using Dual Sequences. VLSI-SOC 2003: 180-185
28		Zion Cien Shen, Chris C. N. Chu: Bounds on the number of slicing, mosaic, and general floorplans. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1354-1361 (2003)
27		Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen: Twin binary sequences: a nonredundant representation for general nonslicing floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 457-469 (2003)
26		Daniel Berleant, Mei-Peng Cheong, Chris C. N. Chu, Yong Guan, Ahmed E. Kamal, Gerald Shedblé, Scott Ferson, James F. Peters: Dependable Handling of Uncertainty. Reliable Computing 9(6): 407-418 (2003)
	2002
25		Chris C. N. Chu, Evangeline F. Y. Young: Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. DATE 2002: 1101
24		Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu: Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. ICCD 2002: 422-427
23		Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109
22		Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen: Twin binary sequences: a non-redundant representation for general non-slicing floorplan. ISPD 2002: 196-201
21		Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho: A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. VLSI Design 2002: 661-
	2001
20		Chris C. N. Chu, D. F. Wong: Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Autom. Electr. Syst. 6(3): 343-371 (2001)
19		Chris C. N. Chu, D. F. Wong: VLSI Circuit Performance Optimization by Geometric Programming. Annals OR 105(1-4): 37-60 (2001)
18		Yu-Yen Mo, Chris C. N. Chu: Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 680-686 (2001)
17		Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong: Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 687-692 (2001)
	2000
16		Yu-Yen Mo, Chris C. N. Chu: A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization. ISPD 2000: 134-139
15		Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong: Floorplan area minimization using Lagrangian relaxation. ISPD 2000: 174-179
	1999
14		Chris C. N. Chu, Martin D. F. Wong: Greedy wire-sizing is linear time. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 398-405 (1999)
13		Chris C. N. Chu, Martin D. F. Wong: A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 787-798 (1999)
12		Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 1014-1025 (1999)
11		Chris C. N. Chu, Martin D. F. Wong: An efficient and optimal algorithm for simultaneous buffer and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1297-1304 (1999)
10		Fung Yu Young, Chris C. N. Chu, D. F. Wong: Generation of Universal Series-Parallel Boolean Functions. J. ACM 46(3): 416-435 (1999)
	1998
9		Chris C. N. Chu, D. F. Wong: A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. DATE 1998: 479-485
8		Chung-Ping Chen, Chris C. N. Chu, D. F. Wong: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ICCAD 1998: 617-624
7		Chris C. N. Chu, D. F. Wong: Greedy wire-sizing is linear time. ISPD 1998: 39-44
6		Chris C. N. Chu, Martin D. F. Wong: A matrix synthesis approach to thermal placement. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1166-1174 (1998)
	1997
5		Chris C. N. Chu, D. F. Wong: A new approach to simultaneous buffer insertion and wire sizing. ICCAD 1997: 614-621
4		Chris C. N. Chu, D. F. Wong: A matrix synthesis approach to thermal placement. ISPD 1997: 163-168
3		Chris C. N. Chu, D. F. Wong: Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ISPD 1997: 192-197
	1996
2		Mee Yee Chan, Francis Y. L. Chin, Chris Chu, Wei-Kei Mak: Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. J. Parallel Distrib. Comput. 33(1): 98-106 (1996)
	1993
1		Mee Yee Chan, Francis Y. L. Chin, Chris Chu, Wai-Kei Mak: Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. SPDP 1993: 285-289

Coauthor Index

1	Arif Ishaq Abou-Seido	[24] [35]
2	Gaurav Ajwani	[74] [79]
3	Charles J. Alpert	[23] [33] [56] [58] [73]
4	Daniel Berleant	[26]
5	Mee Yee Chan	[1] [2]
6	J. Morris Chang	[46]
7	Charlie Chung-Ping Chen (Chung-Ping Chen)	[8] [12]
8	Mei-Peng Cheong	[26]
9	Francis Y. L. Chin (Francis Yuk-Lun Chin)	[1] [2]
10	Royce L. S. Ching	[49]
11	Sampath Dechu	[30] [40] [42] [55]
12	Scott Ferson	[26]
13	Gopal Gandham	[23] [33]
14	Yong Guan	[26]
15	M. L. Ho	[21] [34]
16	Milos Hrkic	[23] [33]
17	Jiang Hu	[23] [33]
18	Ahmed E. Kamal	[26]
19	Chandramouli V. Kashyap	[23] [33]
20	Steve T. W. Lai	[31] [66]
21	Kevin C. K. Leung	[49]
22	Ying-Meng Li	[47]
23	Zhuo Li	[73]
24	Chuan Lin	[52]
25	Yu-Chen Lin	[69]
26	W. S. Luk	[15] [17]
27	Wai-Kei Mak	[1] [69] [74] [75] [78] [79]
28	Wei-Kei Mak	[2]
29	Yu-Yen Mo	[16] [18]
30	Gi-Joon Nam	[58] [73]
31	Brian Nowak	[24] [35]
32	Min Pan	[44] [45] [46] [48] [50] [54] [57] [59] [60] [61]
33	Priyadarshan Patra	[60]
34	James F. Peters	[26]
35	Irith Pomeranz	[29]
36	Stephen T. Quay	[23] [33]
37	Shyam Ramji	[73]
38	Sudhakar M. Reddy	[29]
39	Haoxing Ren	[58]
40	Jarrod A. Roy	[73]
41	Chiu-Wing Sham	[53]
42	Gerald Shedblé	[26]
43	Zion Cien Shen	[22] [27] [28] [39] [40] [42] [47]
44	Debjit Sinha	[37]
45	Yiu-Cheong Tam	[51]
46	Dennis K. Y. Tong	[30] [55]
47	Paul G. Villarrubia (Paul Villarrubia)	[56] [58]
48	Natarajan Viswanathan	[36] [41] [44] [48] [54] [58] [61] [70] [73]
49	Ting-Chi Wang	[69]
50	Martin D. F. Wong (D. F. Wong)	[3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [19] [20]
51	Y. C. Wong	[15] [17]
52	Yiu-Chung Wong	[43] [62]
53	Yue Xu	[64] [67] [71] [76] [77] [81]
54	Jackey Z. Yan	[65] [70] [72] [75] [78] [82]
55	Evangeline F. Y. Young (F. Y. Young, Fung Yu Young)	[10] [15] [17] [21] [22] [25] [27] [30] [31] [32] [34] [49] [51] [53] [55] [66]
56	Yanheng Zhang	[64] [68] [71] [80]
57	Hai Zhou	[37] [45] [52]
58	Wei Zou	[29]

Colors in the list of coauthors

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