Ahsan Raja Chowdhury

	2012
13		Sajib Kumar Mitra, Ahsan Raja Chowdhury: Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis. VLSI Design 2012: 334-339
	2011
12		Ahsan Raja Chowdhury, Madhu Chetty: An improved method to infer Gene Regulatory Network using S-System. IEEE Congress on Evolutionary Computation 2011: 1012-1019
	2010
11		Mir Anamul Hasan, Khaja Md. Sher-E-Alam, Ahsan Raja Chowdhury: Human Disease Diagnosis Using a Fuzzy Expert System CoRR abs/1006.4544: (2010)
	2008
10		Muhammad Ibrahim, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu: Minimization of CTS of k-CNOT Circuits for SSF and MSF Model. DFT 2008: 290-298
9		Ashis Kumer Biswas, Md. Mahmudul Hasan, Moshaddek Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu: A Novel Approach to Design BCD Adder and Carry Skip BCD Adder. VLSI Design 2008: 566-571
8		Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu: Efficient approaches for designing reversible Binary Coded Decimal adders. Microelectronics Journal 39(12): 1693-1703 (2008)
	2006
7		Amin Ahsan Ali, Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury: Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates. CDES 2006: 101-106
6		Ahsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Hasan Babu: A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array. VLSI Design 2006: 311-316
5		Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury: Design of a compact reversible binary coded decimal adder circuit. Journal of Systems Architecture 52(5): 272-282 (2006)
	2005
4		Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury: Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder. VLSI Design 2005: 255-260
	2004
3		Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Haque, Ahsan Raja Chowdhury: A heuristic approach to synthesize Boolean functions using TANT network. ISCAS (2) 2004: 373-376
2		Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury: Synthesis of Full-Adder Circuit Using Reversible Logic. VLSI Design 2004: 757-760
	2003
1		Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury: Reversible Logic Synthesis for Minimization of Full-Adder Circuit. DSD 2003: 50-54

Coauthor Index

1	Amin Ahsan Ali	[7]
2	Hafiz Md. Hasan Babu	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
3	Ashis Kumer Biswas	[8] [9]
4	Madhu Chetty	[12]
5	Syed Mostahed Ali Chowdhury	[1] [2]
6	Md. Anwarul Haque	[3]
7	Md. Mahmudul Hasan	[8] [9]
8	Mir Anamul Hasan	[11]
9	Moshaddek Hasan	[9]
10	Muhammad Ibrahim	[10]
11	Md. Rafiqul Islam	[1] [2] [3]
12	Sajib Kumar Mitra	[13]
13	Rumana Nazmul	[3] [6]
14	Khaja Md. Sher-E-Alam	[11]

Colors in the list of coauthors

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