Paul Chow

	2012
66		Vincent Mirian, Paul Chow: FCache: a system for cache coherent processing on FPGAs. FPGA 2012: 233-236
65		S. Alexander Chin, Paul Chow: OpenCL memory infrastructure for FPGAs (abstract only). FPGA 2012: 269-270
64		Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow: Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms. Int. J. Reconfig. Comp. 2012: (2012)
	2011
63		Paul Chow, Michael J. Wirthlin: IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011, Salt Lake City, Utah, USA, 1-3 May 2011 IEEE Computer Society 2011
62		Charles Lo, Paul Chow: Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI. FPGA 2011: 189-198
61		Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang: Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method. FPL 2011: 110-115
60		Yuanxi Peng, Manuel Saldaña, Paul Chow: Hardware Support for Broadcast and Reduce in MPSoC. FPL 2011: 144-150
59		Alexander Kaganov, Asif Lakhany, Paul Chow: FPGA Acceleration of MultiFactor CDO Pricing. TRETS 4(2): 20 (2011)
58		Lesley Shannon, Paul Chow: Leveraging reconfigurability in the hardware/software codesign process. TRETS 4(3): 28 (2011)
	2010
57		Andrew W. H. House, Manuel Saldaña, Paul Chow: Integrating High-Level Synthesis into MPI. FCCM 2010: 175-178
56		Dharmendra P. Gupta, Paul Chow: Acceleration of an analytical approach to collateralized debt obligation pricing. FPGA 2010: 103-106
55		Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow: Using Partial Reconfiguration in an Embedded Message-Passing System. ReConFig 2010: 418-423
54		Hadi Bannazadeh, Alberto Leon-Garcia, Keith Redmond, G. Tam, A. Khan, M. Ma, S. Dani, Paul Chow: Virtualized Application Networking Infrastructure. TRIDENTCOM 2010: 363-382
53		Manuel Saldaña, Arun Patel, Christopher A. Madill, Daniel Nunes, Danyao Wang, Paul Chow, Ralph Wittig, Henry Styles, Andrew Putnam: MPI as a Programming Model for High-Performance Reconfigurable Computers. TRETS 3(4): 22 (2010)
	2009
52		Paul Chow, Peter Y. K. Cheung: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009 ACM 2009
51		Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose: FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. FCCM 2009: 157-164
50		Daniel L. Ly, Paul Chow: A high-performance FPGA architecture for restricted boltzmann machines. FPGA 2009: 73-82
49		Daniel L. Ly, Paul Chow: A multi-FPGA architecture for stochastic Restricted Boltzmann Machines. FPL 2009: 168-173
48		Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing: Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. ReConFig 2009: 48-53
47		Manuel Saldaña, Emanuel Ramalho, Paul Chow: A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems. Int. J. Reconfig. Comp. 2009: (2009)
	2008
46		Mike Hutton, Paul Chow: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008 ACM 2008
45		Andrew W. H. House, Paul Chow: Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems. FCCM 2008: 291-292
44		Alexander Kaganov, Paul Chow, Asif Lakhany: FPGA acceleration of Monte-Carlo based credit derivative pricing. FPL 2008: 329-334
43		Manuel Saldaña, Emanuel Ramalho, Paul Chow: A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI. ReConFig 2008: 265-270
42		Tor M. Aamodt, Paul Chow: Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy. ACM Trans. Embedded Comput. Syst. 7(3): (2008)
	2007
41		Chichyang Chen, Paul Chow: Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor. ACM Great Lakes Symposium on VLSI 2007: 540-545
40		Sam Lee, Paul Chow: An FPGA Implementation of Reciprocal Sums for SPME. ERSA 2007: 159-165
39		Paul Chow, Mike Hutton: Integrating FPGAs in high-performance computing: introduction. FPGA 2007: 131
38		Tor M. Aamodt, Paul Chow: Optimization of data prefetch helper threads with path-expression based statistical modeling. ICS 2007: 210-221
37		Lesley Shannon, Paul Chow: SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. IEEE Trans. VLSI Syst. 15(4): 377-390 (2007)
36		Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow: Routability of Network Topologies in FPGAs. IEEE Trans. VLSI Syst. 15(8): 948-951 (2007)
	2006
35		Arun Patel, Christopher A. Madill, Manuel Saldaña, Chris Comis, Regis Pomes, Paul Chow: A Scalable FPGA-based Multiprocessor. FCCM 2006: 111-120
34		Manuel Saldaña, Lesley Shannon, Paul Chow: The routability of multiprocessor network topologies in FPGAs. FPGA 2006: 232
33		Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow: A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. FPL 2006: 1-6
32		Manuel Saldaña, Paul Chow: TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs. FPL 2006: 1-6
31		Manuel Saldaña, Lesley Shannon, Paul Chow: The routability of multiprocessor network topologies in FPGAs. SLIP 2006: 49-56
	2005
30		Lesley Shannon, Paul Chow: Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller. FCCM 2005: 63-72
29		Lesley Shannon, Paul Chow: Leveraging Reconfigurability in the Design Process. FPL 2005: 731-732
28		Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow: Designing an FPGA SoC Using a Standardized IP Block Interface. FPT 2005: 341-342
	2004
27		Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow: Reconfigurable Molecular Dynamics Simulator. FCCM 2004: 197-206
26		Lesley Shannon, Paul Chow: Using reconfigurability to achieve real-time profiling for hardware/software codesign. FPGA 2004: 190-199
25		Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow: FPGA-based supercomputing: an implementation for molecular dynamics. FPGA 2004: 253
24		Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen: Hardware Support for Prescient Instruction Prefetch. HPCA 2004: 84-95
	2003
23		Lesley Shannon, Paul Chow: Standardizing the Performance Assessment of Reconfigurable Processor Architectures. FCCM 2003: 282-283
22		Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen: A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS 2003: 13-24
	2001
21		Jorge E. Carrillo, Paul Chow: The effect of reconfigurable units in superscalar processors. FPGA 2001: 141-150
	2000
20		Tor M. Aamodt, Paul Chow: Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. CASES 2000: 128-137
19		L. Louis Zhang, Brent Beacham, Massoud R. Hashemi, Paul Chow, Alberto Leon-Garcia: A Scheduler ASIC for a Programmable Packet Switch. IEEE Micro 20(1): 42-48 (2000)
	1999
18		Ivan Hamer, Paul Chow: DES Cracking on the Transmogrifier 2a. CHES 1999: 13-24
17		Jeffrey A. Jacob, Paul Chow: Memory Interfacing and Instruction Specification for Reconfigurable Processors. FPGA 1999: 145-154
16		Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. International Journal of Parallel Programming 27(5): 327-356 (1999)
	1998
15		David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow: The Transmogrifier-2: a 1 million gate rapid-prototyping system. IEEE Trans. VLSI Syst. 6(2): 188-198 (1998)
	1997
14		David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow: The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. FPGA 1997: 53-61
13		Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: Memory-System Design Considerations for Dynamically-Scheduled Processors. ISCA 1997: 133-143
12		Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: The Multicluster Architecture: Reducing Cycle Time Through Partitioning. MICRO 1997: 149-159
	1996
11		Mazen A. R. Saghir, Paul Chow, Corinna G. Lee: Exploiting Dual Data-Memory Banks in Digital Signal Processors. ASPLOS 1996: 234-243
10		Keith I. Farkas, Norman P. Jouppi, Paul Chow: Register File Design Considerations in Dynamically Scheduled Processors. HPCA 1996: 40-51
	1995
9		Paul Chow, P. Glenn Gulak: A Field-Programmable Mixed-Analog-Digital Array. FPGA 1995: 104-109
8		Keith I. Farkas, Norman P. Jouppi, Paul Chow: How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? HPCA 1995: 78-89
	1994
7		Gennady Feygin, P. Glenn Gulak, Paul Chow: Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. Data Compression Conference 1994: 254-263
6		Gennady Feygin, P. Glenn Gulak, Paul Chow: Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding. Inf. Process. Manage. 30(6): 805-816 (1994)
	1993
5		Gennady Feygin, P. Glenn Gulak, Paul Chow: Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. Data Compression Conference 1993: 118-127
4		Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton: A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS 1993: 1945-1948
3		Gennady Feygin, Patrick G. Gulak, Paul Chow: A multiprocessor architecture for Viterbi decoders with linear speedup. IEEE Transactions on Signal Processing 41(9): 2907-2917 (1993)
	1987
2		Paul Chow, Mark Horowitz: Architectural Tradeoffs in the Design of MIPS-X. ISCA 1987: 300-308
	1983
1		Paul Chow, Zvonko G. Vranesic, Jui Lin Yen: A Pipelined Distributed Arithmetic PFFT Processor. IEEE Trans. Computers 32(12): 1128-1136 (1983)

Coauthor Index

1	Tor M. Aamodt	[20] [22] [24] [38] [42]
2	Navid Azizi	[25] [27]
3	Hadi Bannazadeh	[54]
4	Brent Beacham	[19]
5	Sikang Bian	[36]
6	Jorge E. Carrillo	[21]
7	John Chappel	[4]
8	Chichyang Chen	[41]
9	Peter Y. K. Cheung	[52]
10	S. Alexander Chin	[65]
11	Chris Comis	[35]
12	John Craig	[36]
13	S. Dani	[54]
14	Ahmad Darabiha	[25] [27]
15	Aaron Egier	[25] [27]
16	Keith I. Farkas	[8] [10] [12] [13] [16]
17	Gennady Feygin	[3] [4] [5] [6] [7]
18	Blair Fort	[28] [33]
19	David R. Galloway	[14] [15]
20	Antonio González	[22]
21	Grant Goodes	[4]
22	P. Glenn Gulak	[4] [5] [6] [7] [9]
23	Patrick G. Gulak	[3]
24	Dharmendra P. Gupta	[56]
25	Oswin Hall	[4]
26	Ivan Hamer	[18]
27	Per Hammarlund	[22] [24]
28	Massoud R. Hashemi	[19]
29	Mark Horowitz	[2]
30	Andrew W. H. House	[45] [57]
31	Michael Hutton (Michael D. Hutton, Mike Hutton)	[39] [46]
32	Marcus van Ierssel	[14] [15]
33	Jeffrey A. Jacob	[17]
34	Jiang Jiang	[48] [61]
35	Norman P. Jouppi	[8] [10] [12] [13] [16]
36	Alexander Kaganov	[44] [59]
37	A. Khan	[54]
38	Ian Kuon	[25] [27]
39	Asif Lakhany	[44] [59]
40	Corinna G. Lee	[11]
41	Sam Lee	[40]
42	Alberto Leon-Garcia	[19] [54]
43	David M. Lewis	[14] [15]
44	Yuan Li	[61]
45	Lothar Lilge	[51]
46	Hao Jun Liu	[55] [64]
47	Charles Lo	[62]
48	William Lo	[51]
49	Jason Luu	[51]
50	Daniel L. Ly	[49] [50]
51	M. Ma	[54]
52	Christopher A. Madill	[35] [53]
53	Pedro Marcuello	[22]
54	Vincent Mirian	[48] [66]
55	Daniel Nunes	[53]
56	Samir Parikh	[28] [33]
57	Arun Patel	[28] [33] [35] [53] [55] [64]
58	Yuanxi Peng	[60]
59	Regis Pomes	[35]
60	Andrew Putnam	[53]
61	Emanuel Ramalho	[43] [47]
62	Keith Redmond	[51] [54]
63	Jonathan Rose	[14] [15] [51]
64	Mazen A. R. Saghir	[11]
65	Manuel Saldaña	[28] [31] [32] [33] [34] [35] [36] [43] [47] [53] [55] [57] [60] [64]
66	Ahmad Sayes	[4]
67	Lesley Shannon	[23] [26] [28] [29] [30] [31] [33] [34] [36] [37] [58]
68	John Paul Shen	[22] [24]
69	Satwant Singh	[4]
70	Michael B. Smith	[4]
71	Henry Styles	[53]
72	G. Tam	[54]
73	Kam Pui Tang	[48]
74	Zvonko G. Vranesic	[1] [12] [13] [16]
75	Danyao Wang	[53]
76	Hong Wang	[22] [24]
77	Steven J. E. Wilton	[4]
78	Michael J. Wirthlin	[63]
79	Ralph Wittig	[53]
80	Zuocheng Xing	[48]
81	Jui Lin Yen	[1]
82	Jia Shuo Yue	[36]
83	L. Louis Zhang	[19]
84	Minxuan Zhang	[61]

Colors in the list of coauthors

Last update Tue May 29 01:28:40 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page