 | 2011 |
| 21 |  | Konstantinos Manolopoulos,
Dionisios I. Reisis,
Vassilios A. Chouliaras:
An efficient multiple precision floating-point multiplier.
ICECS 2011: 153-156 |
| 2010 |
| 20 |  | Konstantinos Manolopoulos,
Dionysios I. Reisis,
Vassilios A. Chouliaras:
An efficient dual-mode floating-point Multiply-Add Fused Unit.
ICECS 2010: 5-8 |
| 19 |  | Ludovic A. Krundel,
David J. Mulvaney,
Vassilios A. Chouliaras:
Autonomous Design in VLSI: An In-House Universal Cellular Neural Platform.
ISVLSI 2010: 464-466 |
| 18 |  | Ludovic A. Krundel,
David J. Mulvaney,
Vassilios A. Chouliaras:
Autonomous Design in VLSI: Growing and Learning on Silicon.
ISVLSI 2010: 481-485 |
| 17 |  | Konstantinos Babionitakis,
Vassilios A. Chouliaras,
Konstantinos Manolopoulos,
Kostantinos Nakos,
Dionysios I. Reisis,
Nikolaos Vlassopoulos:
Fully Systolic FFT Architecture for Giga-sample Applications.
Signal Processing Systems 58(3): 281-299 (2010) |
| 2009 |
| 16 |  | Vassilios A. Chouliaras,
Panagiotis Galiatsatos,
Kostantinos Nakos,
Dionysios I. Reisis,
Nikolaos Vlassopoulos:
Efficient cascaded VLSI FFT architecture for OFDM systems.
ICECS 2009: 97-100 |
| 15 |  | Vassilios A. Chouliaras,
Konstantinos Manolopoulos,
Dionysios I. Reisis:
A configurable length, Fused Multiply-Add floating point unit for a VLIW processor.
SoCC 2009: 93-96 |
| 2008 |
| 14 |  | Jia Zheng,
Sijung Hu,
Vassilios A. Chouliaras,
Ron Summers:
Feasibility of Imaging Photoplethysmography.
BMEI (2) 2008: 72-75 |
| 13 |  | Xiaofeng Wu,
Vassilios A. Chouliaras,
José L. Núñez-Yáñez,
R. M. Goodall:
A Novel Delta Sigma Control System Processor and Its VLSI Implementation.
IEEE Trans. VLSI Syst. 16(3): 217-228 (2008) |
| 12 |  | Vassilios A. Chouliaras,
Vincent M. Dwyer,
Shahrukh Agha,
José L. Núñez-Yáñez,
Dionysios I. Reisis,
Kostantinos Nakos,
Konstantinos Manolopoulos:
Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study.
Integration 41(1): 135-152 (2008) |
| 2007 |
| 11 |  | José L. Núñez-Yáñez,
Vassilios A. Chouliaras,
Jiri Gaisler:
Dynamic Voltage Scaling in a FPGA-based System-on-Chip.
FPL 2007: 459-462 |
| 10 |  | Emmanuel Touloupis,
James A. Flint,
Vassilios A. Chouliaras,
David D. Ward:
Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor.
IEEE Trans. Computers 56(12): 1585-1596 (2007) |
| 9 |  | Z. Zhu,
David J. Mulvaney,
Vassilios A. Chouliaras:
Hardware implementation of a novel genetic algorithm.
Neurocomputing 71(1-3): 95-106 (2007) |
| 2006 |
| 8 |  | Xiaofeng Wu,
Vassilios A. Chouliaras,
José L. Núñez-Yáñez,
Roger Goodall,
Tanya Vladimirova:
A Novel Processor Architecture for Real-Time Control.
Asia-Pacific Computer Systems Architecture Conference 2006: 270-280 |
| 2005 |
| 7 |  | Vincent M. Dwyer,
Shahrukh Agha,
Vassilios A. Chouliaras:
Reduced-Bit, Full Search Block-Matching Algorithms and Their Hardware Realizations.
ACIVS 2005: 372-380 |
| 6 |  | Vassilios A. Chouliaras,
Vincent M. Dwyer,
Shahrukh Agha:
On the Performance Improvement of Sub-sampling MPEG-2 Motion Estimation Algorithms with Vector/SIMD Architectures.
ACIVS 2005: 595-602 |
| 5 |  | José L. Núñez-Yáñez,
Vassilios A. Chouliaras:
Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec.
ASAP 2005: 411-416 |
| 4 |  | Vassilios A. Chouliaras,
Tom R. Jacobs,
Ashwin K. Kumaraswamy,
José L. Núñez-Yáñez:
Configurable Multiprocessors for High-Performance MPEG-4 Video Coding.
ISVLSI 2005: 272-273 |
| 3 |  | K. Koutsomyti,
S. R. Parr,
Vassilios A. Chouliaras,
José L. Núñez-Yáñez:
Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards.
SIP 2005: 39-44 |
| 2 |  | José L. Núñez-Yáñez,
Vassilios A. Chouliaras:
A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding.
IEEE Trans. Computers 54(11): 1345-1359 (2005) |
| 2004 |
| 1 |  | Christos Grecos,
Azilah Saparon,
Vassilios A. Chouliaras:
Three novel low complexity scanning orders for MPEG-2 full search motion estimation.
Real-Time Imaging 10(1): 53-65 (2004) |