 | 2011 |
| 17 |  | Xuan-Lun Huang,
Ping-Ying Kang,
Hsiu-Ming Chang,
Jiun-Lang Huang,
Yung-Fa Chou,
Yung-Pin Lee,
Ding-Ming Kwai,
Cheng-Wen Wu:
A self-testing and calibration method for embedded successive approximation register ADC.
ASP-DAC 2011: 713-718 |
| 16 |  | Xuan-Lun Huang,
Ping-Ying Kang,
Jiun-Lang Huang,
Yung-Fa Chou,
Yung-Pin Lee,
Ding-Ming Kwai:
A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager.
European Test Symposium 2011: 39-44 |
| 15 |  | Yu-Jen Huang,
Jin-Fu Li,
Ji-Jan Chen,
Ding-Ming Kwai,
Yung-Fa Chou,
Cheng-Wen Wu:
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs.
VTS 2011: 20-25 |
| 14 |  | Yung-Fa Chou,
Ding-Ming Kwai,
Cheng-Wen Wu:
Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias.
IEEE Trans. VLSI Syst. 19(8): 1346-1356 (2011) |
| 2010 |
| 13 |  | Chang-Tzu Lin,
Ding-Ming Kwai,
Yung-Fa Chou,
Ting-Sheng Chen,
Wen Ching Wu:
CAD reference flow for 3D via-last integrated circuits.
ASP-DAC 2010: 187-192 |
| 12 |  | Che-Wei Chou,
Jin-Fu Li,
Ji-Jan Chen,
Ding-Ming Kwai,
Yung-Fa Chou,
Cheng-Wen Wu:
A Test Integration Methodology for 3D Integrated Circuits.
Asian Test Symposium 2010: 377-382 |
| 11 |  | Jhih-Wei You,
Shi-Yu Huang,
Ding-Ming Kwai,
Yung-Fa Chou,
Cheng-Wen Wu:
Performance Characterization of TSV in 3D IC via Sensitivity Analysis.
Asian Test Symposium 2010: 389-394 |
| 2007 |
| 10 |  | Jen-Chieh Yeh,
Kuo-Liang Cheng,
Yung-Fa Chou,
Cheng-Wen Wu:
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1101-1113 (2007) |
| 2006 |
| 9 |  | Ding-Ming Kwai,
Yung-Fa Chou,
Meng-Fan Chang,
Su-Meng Yang,
Ding-Sheng Chen,
Min-Chung Hsu,
Yu-Zhen Liao,
Shiao-Yi Lin,
Yu-Ling Sung,
Chia-Hsin Lee,
Hsin-Kun Hsu:
FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment.
MTDT 2006: 28-33 |
| 8 |  | Ding-Ming Kwai,
Ching-Hua Hsiao,
Chung-Ping Kuo,
Chi-Hsien Chuang,
Min-Chung Hsu,
Yi-Chun Chen,
Yu-Ling Sung,
Hsien-Yu Pan,
Chia-Hsin Lee,
Meng-Fan Chang,
Yung-Fa Chou:
SRAM Cell Current in Low Leakage Design.
MTDT 2006: 65-70 |
| 2004 |
| 7 |  | Rei-Fu Huang,
Yan-Ting Lai,
Yung-Fa Chou,
Cheng-Wen Wu:
SRAM delay fault modeling and test algorithm development.
ASP-DAC 2004: 104-109 |
| 2003 |
| 6 |  | Rei-Fu Huang,
Yung-Fa Chou,
Cheng-Wen Wu:
Defect Oriented Fault Analysis for SRAM.
Asian Test Symposium 2003: 256-261 |
| 5 |  | Kuo-Liang Cheng,
Chih-Wea Wang,
Jih-Nung Lee,
Yung-Fa Chou,
Chih-Tsun Huang,
Cheng-Wen Wu:
FAME: A Fault-Pattern Based Memory Failure Analysis Framework.
ICCAD 2003: 595-598 |
| 4 |  | Chih-Wea Wang,
Kuo-Liang Cheng,
Jih-Nung Lee,
Yung-Fa Chou,
Chih-Tsun Huang,
Cheng-Wen Wu,
Frank Huang,
Hong-Tzer Yang:
Fault Pattern Oriented Defect Diagnosis for Memories.
ITC 2003: 29-38 |
| 2002 |
| 3 |  | Jen-Chieh Yeh,
Chi-Feng Wu,
Kuo-Liang Cheng,
Yung-Fa Chou,
Chih-Tsun Huang,
Cheng-Wen Wu:
Flash Memory Built-In Self-Test Using March-Like Algorithm.
DELTA 2002: 137-141 |
| 2000 |
| 2 |  | Ding-Ming Kwai,
Hung-Wen Chang,
Hung-Jen Liao,
Ching-Hua Chiao,
Yung-Fa Chou:
etection of SRAM cell stability by lowering array supply voltage.
Asian Test Symposium 2000: 268-273 |
| 1994 |
| 1 |  | Cheng-Wen Wu,
Yung-Fa Chou:
General Modular Multiplication by Block Multiplication and Table Lookup.
ISCAS 1994: 295-298 |