 | 2011 |
|---|
| 8 |       | Jih-Ching Chiu,
Yu-Liang Chou,
Po-Kai Chen,
Ding-Siang Su:
A Unitable Computing Architecture for Chip Multiprocessors.
Comput. J. 54(12): 2033-2052 (2011) |
| 2010 |
|---|
| 7 | | Jih-Ching Chiu,
Yu-Liang Chou,
Ding-Siang Su:
A hyperscalar multi-core architecture.
Conf. Computing Frontiers 2010: 77-78 |
| 6 | | Jih-Ching Chiu,
Yu-Liang Chou,
Po-Kai Chen:
Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture.
ICPP 2010: 277-286 |
| 5 | | Jih-Ching Chiu,
Yu-Liang Chou,
Tseng-Kuei Lin:
The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA.
J. Inf. Sci. Eng. 26(4): 1273-1288 (2010) |
| 4 | | Jih-Ching Chiu,
Yu-Liang Chou:
A multi-streaming SIMD multimedia computing engine.
Microprocessors and Microsystems - Embedded Hardware Design 34(7-8): 247-258 (2010) |
| 2009 |
|---|
| 3 | | Jih-Ching Chiu,
Yu-Liang Chou,
Hua-Yi Tzeng:
A multi-streaming SIMD architecture for multimedia applications.
Conf. Computing Frontiers 2009: 51-60 |
| 2 | | Jih-Ching Chiu,
Kai-Ming Yang,
Yu-Liang Chou:
Design of a novel SIMD architecture by fusing operations and registers.
ICS 2009: 503-504 |
| 2008 |
|---|
| 1 | | Jih-Ching Chiu,
Yu-Liang Chou,
Ren-Bang Lin:
The Multi-context Reconfigurable Processing Unit for Fine-grain Computing.
J. Inf. Sci. Eng. 24(3): 965-979 (2008) |
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