Richard M. Chou

	2001
5		Richard M. Chou, Kewal K. Saluja: Testable Sequential Circuit Design: A Partition and Resynthesis Approach. VTS 2001: 62-67
	1997
4		Richard M. Chou, Kewal K. Saluja: Sequential Circuit Testing: From DFT to SFT. VLSI Design 1997: 274-278
3		Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal: Scheduling tests for VLSI systems under power constraints. IEEE Trans. VLSI Syst. 5(2): 175-185 (1997)
	1995
2		Ning Jiang, Richard M. Chou, Kewal K. Saluja: Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan. FTCS 1995: 41-49
	1994
1		Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal: Power Constraint Scheduling of Tests. VLSI Design 1994: 271-274

Coauthor Index

1	Vishwani D. Agrawal	[1] [3]
2	Ning Jiang	[2]
3	Kewal K. Saluja	[1] [2] [3] [4] [5]

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