Chi-Wen Chou

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2010

3 Ko-Chi Kuo, Chi-Wen Chou: Low power and high speed multiplier design with row bypassing and parallel architecture. Microelectronics Journal 41(10): 639-650 (2010)

2006

2 Ko-Chi Kuo, Chi-Wen Chou: Low Power Multiplier with Bypassing and Tree Strucuture. APCCAS 2006: 602-605

1 Ko-Chi Kuo, Chi-Wen Chou: A Low-Power Multiplier with Bypassing Logic and Operand Decomposition. IMECS 2006: 217-220

	2010
3		Ko-Chi Kuo, Chi-Wen Chou: Low power and high speed multiplier design with row bypassing and parallel architecture. Microelectronics Journal 41(10): 639-650 (2010)
	2006
2		Ko-Chi Kuo, Chi-Wen Chou: Low Power Multiplier with Bypassing and Tree Strucuture. APCCAS 2006: 602-605
1		Ko-Chi Kuo, Chi-Wen Chou: A Low-Power Multiplier with Bypassing Logic and Operand Decomposition. IMECS 2006: 217-220

Coauthor Index

1 Ko-Chi Kuo [1] [2] [3]

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