 | 2010 |
|---|
| 7 |       | Yongtao Wang,
Hamid Mahmoodi,
Lih-Yih Chiou,
Hunsoo Choo,
Jongsun Park,
Woopyo Jeong,
Kaushik Roy:
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering.
Signal Processing Systems 58(2): 125-137 (2010) |
| 2006 |
|---|
| 6 | | Dongku Kang,
Hunsoo Choo,
Khurram Muhammad,
Kaushik Roy:
Layout-driven architecture synthesis for high-speed digital filters.
IEEE Trans. VLSI Syst. 14(2): 203-207 (2006) |
| 2004 |
|---|
| 5 | | Dongku Kang,
Hunsoo Choo,
Kaushik Roy:
Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed.
ICCD 2004: 354-357 |
| 4 | | Hunsoo Choo,
Khurram Muhammad,
Kaushik Roy:
Complexity reduction of digital filters using shift inclusive differential coefficients.
IEEE Transactions on Signal Processing 52(6): 1760-1772 (2004) |
| 2003 |
|---|
| 3 | | Hunsoo Choo,
Khurram Muhammad,
Kaushik Roy:
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters.
DATE 2003: 10700-10705 |
| 2 | | Hunsoo Choo,
Khurram Muhammad,
Kaushik Roy:
Two's complement computation sharing multiplier and its applications to high performance DFE.
IEEE Transactions on Signal Processing 51(2): 458-469 (2003) |
| 2002 |
|---|
| 1 | | Jongsun Park,
Woopyo Jeong,
Hunsoo Choo,
Hamid Mahmoodi-Meimand,
Yongtao Wang,
Kaushik Roy:
High performance and low power FIR filter design based on sharing multiplication.
ISLPED 2002: 295-300 |
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