 | 2012 |
|---|
| 14 |       | Young-Seok Park,
Woo-Young Choi:
On-Chip Compensation of Ring VCO Oscillation Frequency Changes Due to Supply Noise and Process Variation.
IEEE Trans. on Circuits and Systems 59-II(2): 73-77 (2012) |
| 13 | | Kwang-Chun Choi,
Seung-Woo Lee,
Bhum-Cheol Lee,
Woo-Young Choi:
A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector.
IEEE Trans. on Circuits and Systems 59-II(3): 143-147 (2012) |
| 12 | | Chang-Kyung Seong,
Jinsoo Rhim,
Woo-Young Choi:
A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor.
IEEE Trans. on Circuits and Systems 59-II(4): 209-213 (2012) |
| 2011 |
|---|
| 11 | | Young-Seok Park,
Woo-Young Choi:
Supply noise insensitive ring VCO with on-chip adaptive bias-current and voltage-swing control.
ISCAS 2011: 229-232 |
| 10 | | Wang-Soo Kim,
Chang-Kyung Seong,
Woo-Young Choi:
A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms.
ISSCC 2011: 358-359 |
| 2010 |
|---|
| 9 | | Chang-Kyung Seong,
Seung-Woo Lee,
Woo-Young Choi:
A New Network Synchronizer Using Phase Adjustment and Feedforward Filtering Based on Low-Cost Crystal Oscillators.
IEEE T. Instrumentation and Measurement 59(7): 1764-1774 (2010) |
| 8 | | Kwang-Chun Choi,
Minsu Ko,
Duho Kim,
Woo-Young Choi:
Demonstration of 60-GHz Link Using a 1.6-Gb/s Mixed-Mode BPSK Demodulator.
IEICE Transactions 93-C(12): 1704-1707 (2010) |
| 7 | | Young-Seok Park,
Pyung-Su Han,
Woo-Young Choi:
Linear Analysis of Feedforward Ring Oscillators.
IEICE Transactions 93-C(9): 1467-1470 (2010) |
| 2008 |
|---|
| 6 | | Chang-Kyung Seong,
Seung-Woo Lee,
Woo-Young Choi:
A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator.
IEICE Transactions 91-B(5): 1397-1402 (2008) |
| 2007 |
|---|
| 5 | | Myung-Il Roh,
Kyu-Yeul Lee,
Woo-Young Choi:
Rapid generation of the piping model having the relationship with a hull structure in shipbuilding.
Advances in Engineering Software 38(4): 215-228 (2007) |
| 4 | | Chang-Kyung Seong,
Seung-Woo Lee,
Woo-Young Choi:
A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution.
IEICE Transactions 90-C(1): 165-170 (2007) |
| 2006 |
|---|
| 3 | | Pyung-Su Han,
Woo-Young Choi:
1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18µm CMOS.
ISCAS 2006 |
| 2 | | Chang-Kyung Seong,
Seung-Woo Lee,
Woo-Young Choi:
A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution.
ISCAS 2006 |
| 1 | | Ki-Hyuk Lee,
Jae-Wook Lee,
Woo-Young Choi:
A 0.18 µm CMOS 3.125-Gb/s Digitally Controlled Adaptive Line Equalizer with Feed-Forward Swing Control for Backplane Serial Link.
IEICE Transactions 89-C(10): 1454-1459 (2006) |
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