Ken Choi

	2012
16		Haiqing Nan, Li Li, Ken Choi: TDDB-based performance variation of combinational logic in deeply scaled CMOS technology. ISQED 2012: 328-333
15		Yu-Chi Tsao, Ken Choi: Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm. IEEE Trans. VLSI Syst. 20(2): 366-371 (2012)
	2011
14		Yu-Chi Tsao, Ken Choi: Hardware-efficient parallel FIR digital filter structures for symmetric convolutions. ISCAS 2011: 2301-2304
13		Sandeep Sriram, Haiqing Nan, Ken Choi: Low power latch design in near sub-threshold region to improve reliability for soft error. ISQED 2011: 611-614
12		Li Li, Ken Choi, Haiqing Nan: Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously. ISQED 2011: 74-79
11		Haiqing Nan, Kyung Ki Kim, Wei Wang, Ken Choi: Dynamic Voltage and Frequency Scaling for Power- Constrained Design using Process Voltage and Temperature Sensor Circuits. JIPS 7(1): 93-102 (2011)
10		Haiqing Nan, Ken Choi: Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology. Microelectronics Reliability 51(12): 2086-2092 (2011)
	2010
9		Kyung Ki Kim, Haiqing Nan, Ken Choi: Power gating for ultra-low voltage nanometer ICs. ISCAS 2010: 1472-1475
8		Kyung Ki Kim, Haiqing Nan, Ken Choi: Adaptive HCI-aware power gating structure. ISQED 2010: 219-224
7		Kyung Ki Kim, Haiqing Nan, Ken Choi: Hybrid MOSFET/CNFET based power gating structure. SoCC 2010: 334-338
6		Kyung Ki Kim, Wei Wang, Ken Choi: On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits. IEEE Trans. on Circuits and Systems 57-II(10): 798-802 (2010)
	2009
5		Li Li, Ken Choi, Seongmo Park, MooKyung Chung: Selective clock gating by using wasting toggle rate. EIT 2009: 399-404
4		Feng Ge, P. Jain, Ken Choi: Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology. EIT 2009: 405-410
3		Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin: Frequency and yield optimization using power gates in power-constrained designs. ISLPED 2009: 121-126
2		Kyung Ki Kim, Haiqing Nan, Ken Choi: Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage. IEEE Trans. on Circuits and Systems 56-II(12): 926-930 (2009)
	2008
1		Jerry Frenkil, Ken Choi, Kimiyoshi Usami: Power Gating for Ultra-low Leakage: Physics, Design, and Analysis. DATE 2008

Coauthor Index

1	MooKyung Chung	[5]
2	Jerry Frenkil	[1]
3	Feng Ge	[4]
4	Tae Hee Han	[3]
5	P. Jain	[4]
6	Kyung Ki Kim	[2] [6] [7] [8] [9] [11]
7	Nam Sung Kim	[3]
8	Jungseob Lee	[3]
9	Li Li	[5] [12] [16]
10	Haiqing Nan	[2] [7] [8] [9] [10] [11] [12] [13] [16]
11	Seongmo Park	[5]
12	Jun Seomun	[3]
13	Youngsoo Shin	[3]
14	Abhishek A. Sinkar	[3]
15	Sandeep Sriram	[13]
16	Yu-Chi Tsao	[14] [15]
17	Kimiyoshi Usami	[1]
18	Wei Wang	[6] [11]

Colors in the list of coauthors

Last update Tue May 29 01:28:40 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page