Gwan S. Choi

Gwan Choi

	2011
44		Yoon Seok Yang, Pankaj Bhagawat, Gwan Choi: Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system. DAC 2011: 579-584
43		Reeshav Kumar, Yoon Seok Yang, Gwan Choi: Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs. VLSI Design 2011: 238-243
42		Tushar N. K. Jain, Mukund Ramakrishna, Paul V. Gratz, Alexander Sprintson, Gwan Choi: Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1663-1676 (2011)
	2010
41		Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi: Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs. NOCS 2010: 51-58
	2009
40		Pankaj Bhagawat, Rajballav Dash, Gwan S. Choi: Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study. ASP-DAC 2009: 751-756
39		Pankaj Bhagawat, Rajballav Dash, Gwan Choi: Systolic like soft-detection architecture for 4×4 64-QAM MIMO system. DATE 2009: 870-873
38		Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi: SEU hardened clock regeneration circuits. ISQED 2009: 806-813
37		Weihuang Wang, Gwan S. Choi, Kiran K. Gunnam: Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels. VLSI Design 2009: 51-56
36		Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary: Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes". EURASIP J. Emb. Sys. 2009: (2009)
35		Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi: Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. IEEE Trans. VLSI Syst. 17(6): 781-792 (2009)
34		Weihuang Wang, Euncheol Kim, Kiran K. Gunnam, Gwan S. Choi: Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels. J. Low Power Electronics 5(3): 303-312 (2009)
	2008
33		Pankaj Bhagawat, Rajballav Dash, Gwan Choi: Dynamically reconfigurable soft output MIMO detector. ICCD 2008: 68-73
32		Rohit Singhal, Gwan Choi, Rabi N. Mahapatra: Data Handling Limits of On-Chip Interconnects. IEEE Trans. VLSI Syst. 16(6): 707-713 (2008)
	2007
31		Weihuang Wang, Gwan Choi: Minimum-energy LDPC decoder for real-time mobile application. DATE 2007: 343-348
30		Pankaj Bhagawat, Weihuang Wang, Momin Uppal, Gwan Choi, Zixiang Xiong, Mark B. Yeary, Alan Harris: An FPGA Implementation of Dirty Paper Precoder. ICC 2007: 2761-2766
29		Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary, Mohammed Atiquzzaman: VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax. ICC 2007: 4542-4547
28		Kiran K. Gunnam, Gwan Choi, Weihuang Wang, Mark B. Yeary: Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard. ISCAS 2007: 1645-1648
27		Weihuang Wang, Gwan Choi: Speculative Energy Scheduling for LDPC Decoding. ISQED 2007: 79-84
26		Sanghoan Chang, Gwan Choi: Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits. VLSI Design 2007: 109-114
25		Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary: A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes. VLSI Design 2007: 738-743
	2006
24		Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi: A design approach for radiation-hard digital electronics. DAC 2006: 773-778
23		Sanghoan Chang, Gwan Choi: Timing Failure Analysis of Commercial CPUs Under Operating Stress. DFT 2006: 245-253
22		Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra: Information theoretic approach to address delay and reliability in long on-chip interconnects. ICCAD 2006: 310-314
21		Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra: Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk. ISQED 2006: 407-412
20		Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra: Programmable LDPC Decoder Based on the Bubble-Sort Algorithm. VLSI Design 2006: 203-208
	2005
19		Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra: Quantized LDPC decoder design for binary symmetric channels. ISCAS (6) 2005: 5782-5785
	2004
18		Rohit Singhal, Gwan S. Choi, Nathan Mickler, Prabhavati Koteeswaran: Scaleable check node centric architecture for LDPC decoder. ISCAS (4) 2004: 189-192
17		Rajeshwary Tayade, Gwan Choi: Fast Simulation Technique for LDPC Code Analysis. International Conference on Wireless Networks 2004: 707-713
	2003
16		Anand Selvarathinam, Euncheol Kim, Gwan Choi: Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels. ICCD 2003: 520-525
15		Anand Selvarathinam, Gwan Choi, Krishna Narayanan, Achal Prabhakar, Euncheol Kim: A massively scaleable decoder architecture for low-density parity-check codes. ISCAS (2) 2003: 61-64
	2001
14		Zan Yang, Gwan Choi: An On-Line Testing Approach Using Code-Perturbation. IOLTW 2001: 142
13		Zan Yang, Byeong Min, Gwan Choi: Simulation Using Code-Perturbation: Black- and White-Box Approach. ISQED 2001: 44-49
12		Byeong Min, Gwan Choi: ECC: Extended Condition Coverage for Design Verification Using Excitation and Observation. PRDC 2001: 183-190
	2000
11		Zan Yang, Byeong Min, Gwan Choi: Si-emulation: system verification using simulation and emulation. ITC 2000: 160-169
10		Seung H. Hwang, Gwan S. Choi: A Reliability Testing Environment for Off-the-Shelf Memory Subsystems. IEEE Design & Test of Computers 17(3): 116-124 (2000)
9		Byeong Min, Gwan Choi: Verification Simulation Acceleration Using Code-Perturbation. J. Electronic Testing 16(1-2): 83-90 (2000)
	1998
8		Ronjeet Lal, Gwan S. Choi: Error and Failure Analysis of a UNIX Server. HASE 1998: 232-239
7		Seung H. Hwang, Gwan S. Choi: On-Chip Cache Memory Resilience. HASE 1998: 240-247
	1996
6		Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi: A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. IEEE Trans. Computers 45(11): 1248-1256 (1996)
	1994
5		Gregory L. Ries, Gwan S. Choi, Ravishankar K. Iyer: Device-Level Transient Fault Modeling. FTCS 1994: 86-94
	1993
4		Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer: A Fast and Accurate Gate-Level Transient Fault Simulation Environment. FTCS 1993: 310-319
3		Gwan S. Choi, Ravishankar K. Iyer: Wear-Out Simulation Environment for VLSI Designs. FTCS 1993: 320-329
2		Gwan S. Choi, Ravishankar K. Iyer, Daniel G. Saab: Fault behavior dictionary for simulation of device-level transients. ICCAD 1993: 6-9
	1992
1		Gwan S. Choi, Ravishankar K. Iyer: FOCUS: An Experimental Environment for Fault Sensitivity Analysis. IEEE Trans. Computers 41(12): 1515-1526 (1992)

Coauthor Index

1	Mohammed Atiquzzaman	[29]
2	Pankaj Bhagawat	[30] [33] [39] [40] [44]
3	Hungse Cha	[4] [6]
4	Sanghoan Chang	[23] [26]
5	Rajballav Dash	[33] [38] [39] [40]
6	Rajesh Garg	[24] [35] [38]
7	Paul Gratz (Paul V. Gratz)	[41] [42]
8	Kiran K. Gunnam	[25] [28] [29] [34] [36] [37]
9	Alan Harris	[30]
10	Seung H. Hwang	[7] [10]
11	Ravishankar K. Iyer (Ravi K. Iyer)	[1] [2] [3] [4] [5] [6]
12	Tushar N. K. Jain	[41] [42]
13	Nikhil Jayakumar	[24] [35]
14	Sunil P. Khatri	[24] [35] [38]
15	Euncheol Kim	[15] [16] [34]
16	Prabhavati Koteeswaran	[18]
17	Reeshav Kumar	[43]
18	Ronjeet Lal	[8]
19	Rabi N. Mahapatra	[19] [20] [21] [22] [32]
20	Nathan Mickler	[18]
21	Byeong Min	[9] [11] [12] [13]
22	Krishna Narayanan	[15]
23	Janak H. Patel	[4] [6]
24	Achal Prabhakar	[15]
25	Mukund Ramakrishna	[42]
26	Gregory L. Ries	[5]
27	Elizabeth M. Rudnick	[4] [6]
28	Daniel G. Saab	[2]
29	Anand Selvarathinam	[15] [16]
30	Rohit Singhal	[18] [19] [20] [21] [22] [32]
31	Alexander Sprintson (Alex Sprintson)	[41] [42]
32	Rajeshwary Tayade	[17]
33	Momin Uppal	[30]
34	Weihuang Wang	[27] [28] [30] [31] [34] [37]
35	Zixiang Xiong	[30]
36	Yoon Seok Yang	[43] [44]
37	Zan Yang	[11] [13] [14]
38	Mark B. Yeary	[25] [28] [29] [30] [36]

Colors in the list of coauthors

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