Seongjae Cho

	2011
13		Gil Sung Lee, Doo-Hyun Kim, Seongjae Cho, Byung-Gook Park: A New 1T DRAM Cell: Cone Type 1T DRAM Cell. IEICE Transactions 94-C(5): 681-685 (2011)
	2010
12		Dong-Seup Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jung Han Lee, Seongjae Cho, Byung-Gook Park: Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer. IEICE Transactions 93-C(5): 540-545 (2010)
11		Seongjae Cho, Jung Hoon Lee, Yoon Kim, Jang-Gn Yun, Hyungcheol Shin, Byung-Gook Park: Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices. IEICE Transactions 93-C(5): 596-601 (2010)
	2009
10		Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park: Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL). IEICE Transactions 92-C(5): 620-626 (2009)
9		Sang Hyuk Park, Sangwoo Kang, Seongjae Cho, Dong-Seup Lee, Jung Han Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jong Duk Lee, Byung-Gook Park: Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation. IEICE Transactions 92-C(5): 647-652 (2009)
8		Yoon Kim, Seongjae Cho, Gil Sung Lee, Il Han Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park: 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array. IEICE Transactions 92-C(5): 653-658 (2009)
7		Doo-Hyun Kim, Il Han Park, Seongjae Cho, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park: Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory. IEICE Transactions 92-C(5): 659-663 (2009)
6		Byung-Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, Seongjae Cho: Nanosculpture: Three-dimensional CMOS device structures for the ULSI era. Microelectronics Journal 40(4-5): 769-772 (2009)
	2008
5		Seongjae Cho, Il Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park: Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI). IEICE Transactions 91-C(5): 731-735 (2008)
4		Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung-Gook Park: Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme. IEICE Transactions 91-C(5): 742-746 (2008)
	2007
3		Hochul Lee, Youngchang Yoon, Seongjae Cho, Hyungcheol Shin: Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs. IEICE Transactions 90-C(5): 968-972 (2007)
2		Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, Byung-Gook Park: Design and Simulation of Asymmetric MOSFETs. IEICE Transactions 90-C(5): 978-982 (2007)
1		Seongjae Cho, Jang-Gn Yun, Il Han Park, Jung Hoon Lee, Jong Pil Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park: Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices. IEICE Transactions 90-C(5): 988-993 (2007)

Coauthor Index

1	Woo Young Choi	[2]
2	Hoon Jeong	[6]
3	Kwon-Chil Kang	[9] [12]
4	Sangwoo Kang	[9]
5	Doo-Hyun Kim	[4] [5] [7] [13]
6	Jong Pil Kim	[1] [2] [6]
7	Sang Wan Kim	[2]
8	Yoon Kim	[4] [8] [11]
9	Dong-Seup Lee	[9] [12]
10	Gil Sung Lee	[4] [8] [10] [13]
11	Hochul Lee	[3]
12	Jong Duk Lee	[1] [2] [4] [5] [7] [8] [9] [10]
13	Joung-Eob Lee	[9] [12]
14	Jung Han Lee	[9] [12]
15	Jung Hoon Lee	[1] [4] [5] [6] [10] [11]
16	Byung-Gook Park	[1] [2] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
17	Il Han Park	[1] [4] [5] [7] [8]
18	Sang Hyuk Park	[9]
19	Hyungcheol Shin	[1] [3] [5] [7] [8] [10] [11]
20	Jae Young Song	[2] [6]
21	Hong-Seon Yang	[9] [12]
22	Youngchang Yoon	[3]
23	Jang-Gn Yun	[1] [4] [5] [11]

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page