 | 2012 |
| 22 |  | Ken Chang,
SeongHwan Cho:
Session 19 overview: 20+ Gb/s wireline transceivers and injection-locked clocking: Wireline subcommittee.
ISSCC 2012: 322-323 |
| 21 |  | Pyoungwon Park,
Jaejin Park,
Hojin Park,
SeongHwan Cho:
An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS.
ISSCC 2012: 336-337 |
| 20 |  | Dongmin Park,
SeongHwan Cho:
A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS.
ISSCC 2012: 344-346 |
| 19 |  | Ichiro Fujimori,
SeongHwan Cho,
Joshua Friedrich,
John Stonick:
Optical PCB interconnects, Niche or mainstream?
ISSCC 2012: 516 |
| 18 |  | Jaewon Lee,
Woojae Lee,
SeongHwan Cho:
A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS.
IEEE Trans. on Circuits and Systems 59-I(1): 124-136 (2012) |
| 2011 |
| 17 |  | Pyoungwon Park,
Dongmin Park,
SeongHwan Cho:
A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL.
CICC 2011: 1-4 |
| 16 |  | Jaewook Kim,
Wonsik Yu,
Hyun-Kyu Yu,
SeongHwan Cho:
A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS.
ISSCC 2011: 176-178 |
| 15 |  | Joonhee Lee,
Sunghyun Park,
SeongHwan Cho:
A 470-µW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme.
IEEE Trans. VLSI Syst. 19(1): 61-70 (2011) |
| 2010 |
| 14 |  | Woojae Lee,
SeongHwan Cho:
A 2.4-GHz reference doubled fractional-N PLL with dual phase detector in 0.13-μm CMOS.
ISCAS 2010: 1328-1331 |
| 13 |  | Sung-Pah Lee,
SeongHwan Cho:
A background KDCO compensation technique for constant bandwidth in all-digital phase-locked loop.
ISCAS 2010: 3401-3404 |
| 12 |  | Young-Hwa Kim,
Jaewon Lee,
SeongHwan Cho:
A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages.
ISCAS 2010: 4041-4044 |
| 11 |  | Jaewook Kim,
Tae-Kwang Jang,
Young-Gyu Yoon,
SeongHwan Cho:
Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter.
IEEE Trans. on Circuits and Systems 57-I(1): 18-30 (2010) |
| 10 |  | Sung-Jin Kim,
Min-Chang Cho,
SeongHwan Cho:
An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder.
IEICE Transactions 93-C(6): 785-795 (2010) |
| 2009 |
| 9 |  | Sunghyun Park,
Changwook Min,
SeongHwan Cho:
A 95nW Ring Oscillator-based Temperature Sensor for RFID Tags in 0.13µm CMOS.
ISCAS 2009: 1153-1156 |
| 8 |  | Min-Chang Cho,
Jee-Yeon Kim,
SeongHwan Cho:
A Bio-impedance Measurement System for Portable Monitoring of Heart Rate and Pulse Wave Velocity using Small Body Area.
ISCAS 2009: 3106-3109 |
| 7 |  | Joonhee Lee,
Sungjun Kim,
Sehyung Jeon,
Woojae Lee,
SeongHwan Cho:
A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS.
IEICE Transactions 92-C(4): 589-591 (2009) |
| 2008 |
| 6 |  | Sung-Jin Kim,
Min-Chang Cho,
Joonhyun Park,
Kisuk Song,
Yul Kim,
SeongHwan Cho:
An ultra low power UHF RFID tag front-end for EPCglobal Gen2 with novel clock-free decoder.
ISCAS 2008: 660-663 |
| 5 |  | Young-Gyu Yoon,
Jaewook Kim,
Tae-Kwang Jang,
SeongHwan Cho:
A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators.
IEEE Trans. on Circuits and Systems 55-I(11): 3571-3581 (2008) |
| 2006 |
| 4 |  | Dongmin Park,
SeongHwan Cho:
A power-optimized CMOS LC VCO with wide tuning range in 0.5-V supply.
ISCAS 2006 |
| 3 |  | Jaewook Kim,
SeongHwan Cho:
A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator.
ISCAS 2006 |
| 2 |  | Jaewon Lee,
SeongHwan Cho:
A Low Power Transmitter for Phase-Shift Keying Modulation Schemes.
PIMRC 2006: 1-5 |
| 2005 |
| 1 |  | SeongHwan Cho,
Sungmin Ock,
Sang-Hoon Lee,
Joonsuk Lee:
A low power pipelined analog-to-digital converter using series sampling capacitors.
ISCAS (6) 2005: 6178-6181 |