Junho Cho

	2011
15		Hyunwoo Ji, Junho Cho, Wonyong Sung: Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU. Signal Processing Systems 64(1): 149-159 (2011)
	2010
14		Junho Cho, Wonyong Sung: Adaptive Threshold Technique for Bit-Flipping Decoding of Low-Density Parity-Check Codes. IEEE Communications Letters 14(9): 857-859 (2010)
13		Junho Cho, Jonghong Kim, Wonyong Sung: VLSI Implementation of a High-Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes. IEEE Trans. on Circuits and Systems 57-I(5): 1083-1094 (2010)
	2009
12		Junho Cho, Jonghong Kim, Hyunwoo Ji, Wonyong Sung: VLSI Implementation of a Soft Bit-flipping Decoder for PG-LDPC Codes. ISCAS 2009: 908-911
11		Junho Cho, Naresh R. Shanbhag, Wonyong Sung: Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard. SiPS 2009: 040-045
10		Jae-Woo Ahn, Hoseok Chang, Junho Cho, Wonyong Sung: SIMD processor based implementation of recursive filtering equations. SiPS 2009: 087-092
9		Hyunwoo Ji, Junho Cho, Wonyong Sung: Massively parallel implementation of cyclic LDPC codes on a general purpose graphics processing unit. SiPS 2009: 285-290
8		Junho Cho, Wonyong Sung: Efficient Software-Based Encoding and Decoding of BCH Codes. IEEE Trans. Computers 58(7): 878-889 (2009)
7		Hoseok Chang, Junho Cho, Wonyong Sung: Compiler-Based Performance Evaluation of an SIMD Processor with a Multi-Bank Memory Unit. Signal Processing Systems 56(2-3): 249-260 (2009)
	2008
6		Junho Cho, Wonyong Sung: Software implementation of Chien search process for strong BCH codes. ISCAS 2008: 1842-1845
5		Junho Cho, Wonyong Sung: Strength-Reduced Parallel Chien Search Architecture for Strong BCH Codes. IEEE Trans. on Circuits and Systems 55-II(5): 427-431 (2008)
	2007
4		Chulhan Lee, Junho Cho, Kyoungsu Oh: Visual Hull with Silhouette Maps. HCI (14) 2007: 88-96
	2006
3		Junho Cho, Hoseok Chang, Wonyong Sung: An FPGA based SIMD processor with a vector memory unit. ISCAS 2006
2		Hoseok Chang, Junho Cho, Wonyong Sung: Performance Evaluation of an SIMD Architecture with a Multi-bank Vector Memory Unit. SiPS 2006: 71-76
1		Chulhan Lee, Junho Cho, Kyoungsu Oh: Hardware-accelerated jaggy-free visual hulls with silhouette maps. VRST 2006: 87-90

Coauthor Index

1	Jae-Woo Ahn	[10]
2	Hoseok Chang	[2] [3] [7] [10]
3	Hyunwoo Ji	[9] [12] [15]
4	Jonghong Kim	[12] [13]
5	Chulhan Lee	[1] [4]
6	Kyoungsu Oh	[1] [4]
7	Naresh R. Shanbhag	[11]
8	Wonyong Sung	[2] [3] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]

Colors in the list of coauthors

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