 | 2008 |
|---|
| 10 |       | Shingo Watanabe,
Akihiro Chiyonobu,
Toshinori Sato:
A Low-Power Instruction Issue Queue for Microprocessors.
IEICE Transactions 91-C(4): 400-409 (2008) |
| 2007 |
|---|
| 9 | | Shingo Watanabe,
Akihiro Chiyonobu,
Toshinori Sato:
Indirect Tag Search Mechanism for Instruction Window Energy Reduction.
CIT 2007: 841-846 |
| 8 | | Yuji Kunitake,
Akihiro Chiyonobu,
Koichiro Tanaka,
Toshinori Sato:
Challenges in Evaluations for a Typical-Case Design Methodology.
ISQED 2007: 374-379 |
| 7 |  | Toshinori Sato,
Yuu Tanaka,
Hidenori Sato,
Toshimasa Funaki,
Takenori Koushiro,
Akihiro Chiyonobu:
Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism.
I. J. Comput. Appl. 14(2): 79-91 (2007) |
| 2006 |
|---|
| 6 | | Toshinori Sato,
Yuu Tanaka,
Hidenori Sato,
Toshimasa Funaki,
Takenori Koushiro,
Akihiro Chiyonobu:
Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors.
PATMOS 2006: 553-562 |
| 5 | | Toshinori Sato,
Akihiro Chiyonobu:
Evaluating the Impact of Fault Recovery on Superscalar Processor Performance.
PRDC 2006: 369-370 |
| 4 | | Seiichiri Fujii,
Akihito Sakanaka,
Akihiro Chiyonobu,
Toshinori Sato:
A leakage-energy-reduction technique for cache memories in embedded processors.
J. Embedded Computing 2(1): 49-55 (2006) |
| 3 | | Akihiro Chiyonobu,
Toshinori Sato:
Energy-efficient instruction scheduling utilizing cache miss information.
SIGARCH Computer Architecture News 34(1): 65-70 (2006) |
| 2005 |
|---|
| 2 | | Toshinori Sato,
Akihiro Chiyonobu:
An Energy-Efficient Clustered Superscalar Processor.
IEICE Transactions 88-C(4): 544-551 (2005) |
| 2004 |
|---|
| 1 | | Akihiro Chiyonobu,
Toshinori Sato:
Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture.
ISICT 2004: 190-195 |
Data released under the ODC-BY 1.0 license — See also our legal information page