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| 2001 | ||
|---|---|---|
| 1 | Po-Xun Chiu, Yu-Chung Lin, Yi-Ling Hsieh, Tsai-Ming Hsieh: Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint. ISCAS (5) 2001: 519-522 | |
| 1 | Tsai-Ming Hsieh | [1] |
| 2 | Yi-Ling Hsieh | [1] |
| 3 | Yu-Chung Lin | [1] |
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