Gordon R. Chiu

	2007
3		Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown: Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. VLSI Syst. 15(8): 895-903 (2007)
	2006
2		Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown: Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD 2006: 135-142
1		Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown: Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP 2006: 3-8

Coauthor Index

1	Stephen Dean Brown	[1] [2] [3]
2	Valavan Manohararajah	[1] [2] [3]
3	Deshanand P. Singh	[1] [2] [3]

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