 | 2011 |
| 12 |  | Alaa R. Alameldeen,
Ilya Wagner,
Zeshan Chishti,
Wei Wu,
Chris Wilkerson,
Shih-Lien Lu:
Energy-efficient cache design using variable-strength error-correcting codes.
ISCA 2011: 461-472 |
| 11 |  | Alaa R. Alameldeen,
Zeshan Chishti,
Chris Wilkerson,
Wei Wu,
Shih-Lien Lu:
Adaptive Cache Design to Enable Reliable Low-Voltage Operation.
IEEE Trans. Computers 60(1): 50-63 (2011) |
| 2010 |
| 10 |  | Chris Wilkerson,
Alaa R. Alameldeen,
Zeshan Chishti,
Wei Wu,
Dinesh Somasekhar,
Shih-Lien Lu:
Reducing cache power with low-cost, multi-bit error-correcting codes.
ISCA 2010: 83-93 |
| 9 |  | Ahmed M. Amin,
Zeshan Chishti:
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency.
ISLPED 2010: 383-388 |
| 2009 |
| 8 |  | Zeshan Chishti,
Alaa R. Alameldeen,
Chris Wilkerson,
Wei Wu,
Shih-Lien Lu:
Improving cache lifetime reliability at ultra-low voltages.
MICRO 2009: 89-99 |
| 7 |  | Chris Wilkerson,
Hongliang Gao,
Alaa R. Alameldeen,
Zeshan Chishti,
Muhammad M. Khellah,
Shih-Lien Lu:
Trading Off Cache Capacity for Low-Voltage Operation.
IEEE Micro 29(1): 96-103 (2009) |
| 2008 |
| 6 |  | Chris Wilkerson,
Hongliang Gao,
Alaa R. Alameldeen,
Zeshan Chishti,
Muhammad M. Khellah,
Shih-Lien Lu:
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation.
ISCA 2008: 203-214 |
| 5 |  | Eric Chun,
Zeshan Chishti,
T. N. Vijaykumar:
Shapeshifter: Dynamically changing pipeline width and speed to address process variations.
MICRO 2008: 411-422 |
| 4 |  | Zeshan Chishti,
T. N. Vijaykumar:
Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies.
IEEE Trans. Computers 57(1): 69-81 (2008) |
| 2005 |
| 3 |  | Zeshan Chishti,
Michael D. Powell,
T. N. Vijaykumar:
Optimizing Replication, Communication, and Capacity Allocation in CMPs.
ISCA 2005: 357-368 |
| 2004 |
| 2 |  | T. N. Vijaykumar,
Zeshan Chishti:
Wire Delay is Not a Problem for SMT (In the Near Future).
ISCA 2004: 40-51 |
| 2003 |
| 1 |  | Zeshan Chishti,
Michael D. Powell,
T. N. Vijaykumar:
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures.
MICRO 2003: 55-66 |