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 | 2012 | |
|---|---|---|
| 7 |      | Doru-Florin Chiper: Radix-2 Fast Algorithm for Computing Discrete Hartley Transform of Type III. IEEE Trans. on Circuits and Systems 59-II(5): 297-301 (2012) |
| 2011 | ||
| 6 | | Doru-Florin Chiper: A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure. Central Europ. J. Computer Science 1(2): 243-250 (2011) |
| 5 | | Doru-Florin Chiper, Paul Ungureanu: Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT. EURASIP J. Adv. Sig. Proc. 2011: (2011) |
| 4 | | Doru-Florin Chiper: Fast Radix-2 Algorithm for the Discrete Hartley Transform of Type II. IEEE Signal Process. Lett. 18(11): 687-689 (2011) |
| 2007 | ||
| 3 | | Doru-Florin Chiper, M. N. S. Swamy, M. Omair Ahmad: An Efficient Unified Framework for Implementation of a Prime-Length DCT/IDCT With High Throughput. IEEE Transactions on Signal Processing 55(6-2): 2925-2936 (2007) |
| 2002 | ||
| 2 | | Doru-Florin Chiper, M. N. S. Swamy, M. Omair Ahmad, Thanos Stouraitis: A systolic array architecture for the discrete sine transform. IEEE Transactions on Signal Processing 50(9): 2347-2354 (2002) |
| 1999 | ||
| 1 |  | Doru-Florin Chiper: A Systolic Array Algorithm for an Efficient Unified Memory-Based Implementation of the Inverse Discrete Cosine and Sine Transforms. ICIP (2) 1999: 764-768 |
| 1 | M. Omair Ahmad | [2] [3] |
| 2 | Thanos Stouraitis | [2] |
| 3 | M. N. S. Swamy | [2] [3] |
| 4 | Paul Ungureanu | [5] |
Colors in the list of coauthors
Last update Tue May 29 20:41:18 2012 CET by the DBLP Team —
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