 | 2011 |
| 10 |  | Yi-Siou Chen,
Lih-Yih Chiou,
Hsun-Hsiang Chang:
A fast and effective dynamic trace-based method for analyzing architectural performance.
ASP-DAC 2011: 591-596 |
| 2010 |
| 9 |  | Shien-Chun Luo,
Lih-Yih Chiou:
A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing.
IEEE Trans. on Circuits and Systems 57-II(6): 440-445 (2010) |
| 8 |  | Yongtao Wang,
Hamid Mahmoodi,
Lih-Yih Chiou,
Hunsoo Choo,
Jongsun Park,
Woopyo Jeong,
Kaushik Roy:
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering.
Signal Processing Systems 58(2): 125-137 (2010) |
| 2009 |
| 7 |  | Lih-Yih Chiou,
Shien-Chun Luo:
Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics.
IEEE Trans. VLSI Syst. 17(11): 1659-1663 (2009) |
| 6 |  | Lih-Yih Chiou,
Yi-Siou Chen,
Chih-Hsien Lee:
System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(8): 1213-1223 (2009) |
| 2007 |
| 5 |  | Lih-Yih Chiou,
Shien-Chun Luo:
An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop.
ISCAS 2007: 1157-1160 |
| 2006 |
| 4 |  | Yen-Ting Liu,
Lih-Yih Chiou,
Soon-Jyh Chang:
Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop.
ISCAS 2006 |
| 2005 |
| 3 |  | Lih-Yih Chiou,
Swarup Bhunia,
Kaushik Roy:
Synthesis of application-specific highly efficient multi-mode cores for embedded systems.
ACM Trans. Embedded Comput. Syst. 4(1): 168-188 (2005) |
| 2003 |
| 2 |  | Lih-Yih Chiou,
Swarup Bhunia,
Kaushik Roy:
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications.
DATE 2003: 10096-10103 |
| 2002 |
| 1 |  | Mark C. Johnson,
Dinesh Somasekhar,
Lih-Yih Chiou,
Kaushik Roy:
Leakage control with efficient use of transistor stacks in single threshold CMOS.
IEEE Trans. VLSI Syst. 10(1): 1-5 (2002) |