Scott Y. L. Chin

	2011
6		Scott Y. L. Chin, Steven J. E. Wilton: Towards scalable FPGA CAD through architecture. FPGA 2011: 143-152
	2009
5		Scott Y. L. Chin, Steven J. E. Wilton: An analytical model relating FPGA architecture and place and route runtime. FPL 2009: 146-153
4		Scott Y. L. Chin, Steven J. E. Wilton: Improving the memory footprint and runtime scalability of FPGA CAD algorithms. FPL 2009: 717-718
3		Scott Y. L. Chin, Steven J. E. Wilton: Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms. TRETS 1(4): (2009)
	2008
2		Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton: On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays. Int. J. Reconfig. Comp. 2008: (2008)
	2006
1		Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton: Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. FPL 2006: 1-8

Coauthor Index

1	Clarence S. P. Lee	[1] [2]
2	Steven J. E. Wilton	[1] [2] [3] [4] [5] [6]

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