 | 2012 |
| 29 |  | Robin Bonamy,
Hung-Manh Pham,
Sébastien Pillement,
Daniel Chillet:
UPaRC - Ultra-fast power-aware reconfiguration controller.
DATE 2012: 1373-1378 |
| 2011 |
| 28 |  | Antoine Eiche,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
Parallel Evaluation of Hopfield Neural Networks.
IJCCI (NCTA) 2011: 248-253 |
| 27 |  | Robin Bonamy,
Daniel Chillet,
Olivier Sentieys,
Sebastien Bilavarn:
Towards a power and energy efficient use of partial dynamic reconfiguration.
ReCoSoC 2011: 1-4 |
| 26 |  | Surya Narayanan,
Daniel Chillet,
Sébastien Pillement,
Ioannis Sourdis:
Hardware OS Communication Service and Dynamic Memory Management for RSoCs.
ReConFig 2011: 117-122 |
| 25 |  | Surya Narayanan,
Ludovic Devaux,
Daniel Chillet,
Sébastien Pillement,
Ioannis Sourdis:
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources.
VLSI-SoC 2011: 196-199 |
| 24 |  | Dominique Blouin,
Daniel Chillet,
Eric Senn,
Sebastien Bilavarn,
Robin Bonamy,
Christian Samoyeau:
AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC.
Int. J. Reconfig. Comp. 2011: (2011) |
| 23 |  | Daniel Chillet,
Antoine Eiche,
Sébastien Pillement,
Olivier Sentieys:
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network.
Journal of Systems Architecture - Embedded Systems Design 57(4): 340-353 (2011) |
| 22 |  | Robin Bonamy,
Daniel Chillet,
Olivier Sentieys,
Sebastien Bilavarn:
Parallelism Level Impact on Energy Consumption in Reconfigurable Devices.
SIGARCH Computer Architecture News 39(4): 104-105 (2011) |
| 2010 |
| 21 |  | Antoine Eiche,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
Task placement for dynamic and partial reconfigurable architecture.
DASIP 2010: 228-234 |
| 20 |  | Daniel Chillet:
Open-People: Open Power and Energy Optimization PLatform and Estimator.
PATMOS 2010: 251 |
| 19 |  | Ludovic Devaux,
Sébastien Pillement,
Daniel Chillet,
Didier Demigny:
R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip.
ReConFig 2010: 376-381 |
| 18 |  | Ludovic Devaux,
Sana Ben Sassi,
Sébastien Pillement,
Daniel Chillet,
Didier Demigny:
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures.
Int. J. Reconfig. Comp. 2010: (2010) |
| 2009 |
| 17 |  | Sébastien Pillement,
Daniel Chillet,
Yaset Oliva,
Jean-Christophe Prévotet:
High-Level Exploration for Dynamic Reconfiguration Management.
ERSA 2009: 301-302 |
| 16 |  | Benoit Miramond,
Emmanuel Huck,
François Verdier,
Mohamed El Amine Benkhelifa,
Bertrand Granado,
Thomas LeFebvre,
Mehdi Aïchouch,
Jean-Christophe Prévotet,
Yaset Oliva,
Daniel Chillet,
Sébastien Pillement:
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms.
Int. J. Reconfig. Comp. 2009: (2009) |
| 2008 |
| 15 |  | Jean-Christophe Prévotet,
Mohamed El Amine Benkhelifa,
Bertrand Granado,
Emmanuel Huck,
Benoit Miramond,
François Verdier,
Daniel Chillet,
Sébastien Pillement:
A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources.
ReConFig 2008: 61-66 |
| 14 |  | Daniel Chillet,
Raphaël David,
E. Grâce,
Olivier Sentieys:
Structure mémoire reconfigurable. Vers une structure de stockage faible consommation.
Technique et Science Informatiques 27(1-2): 181-202 (2008) |
| 2007 |
| 13 |  | Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures.
IJCNN 2007: 102-107 |
| 2006 |
| 12 |  | Daniel Menard,
Daniel Chillet,
Olivier Sentieys:
Floating-to-Fixed-Point Conversion for Digital Signal Processors.
EURASIP J. Adv. Sig. Proc. 2006: (2006) |
| 2005 |
| 11 |  | Frank Hannig,
Hritam Dutta,
Alexey Kupriyanov,
Jürgen Teich,
Rainer Schaffer,
Sebastian Siegel,
Renate Merker,
Ronan Keryell,
Bernard Pottier,
Daniel Chillet,
Daniel Menard,
Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures.
ReCoSoC 2005: 27-34 |
| 10 |  | François Verdier,
Jean-Christophe Prévotet,
Mohamed El Amine Benkhelifa,
Daniel Chillet,
Sébastien Pillement:
Exploring RTOS issues with a high-level model of a reconfigurable SoC platform.
ReCoSoC 2005: 71-78 |
| 2003 |
| 9 |  | Daniel Menard,
Taofik Saïdi,
Daniel Chillet,
Olivier Sentieys:
Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe.
Technique et Science Informatiques 22(6): 783-803 (2003) |
| 2002 |
| 8 |  | Daniel Menard,
Daniel Chillet,
François Charot,
Olivier Sentieys:
Automatic floating-point to fixed-point conversion for DSP code generation.
CASES 2002: 270-276 |
| 7 |  | Raphaël David,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
A Compilation Framework for a Dynamically Reconfigurable Architecture.
FPL 2002: 1058-1067 |
| 6 |  | Raphaël David,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints.
IPDPS 2002 |
| 5 |  | Sébastien Pillement,
Daniel Chillet,
Olivier Sentieys:
Behavioral IP Specification and Integration Framework for High-Level Design Reuse.
ISQED 2002: 388-393 |
| 2001 |
| 4 |  | Raphaël David,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals.
VLSI-SOC 2001: 51-62 |
| 2000 |
| 3 |  | Jean-Philippe Diguet,
Daniel Chillet,
Olivier Sentieys:
A Framework for High Level Estimations of Signal Processing VLSI Implementations.
VLSI Signal Processing 25(3): 261-284 (2000) |
| 1999 |
| 2 |  | Daniel Chillet,
Olivier Sentieys,
Michel Corazza:
Memory Unit Design for Real Time DSP Applications.
Great Lakes Symposium on VLSI 1999: 260- |
| 1 |  | J. O. Dedou,
Daniel Chillet,
Olivier Sentieys:
Behavioral synthesis of asynchronous systems: a methodology.
ISCAS (6) 1999: 370-373 |