Feng-Tso Chien

	2012
6		Chao-Hung Chen, Hsien-Chin Chiu, Chih-Wei Yang, Jeffrey S. Fu, Feng-Tso Chien: Novel GaAs enhancement-mode/depletion-mode pHEMTs technology using high-k praseodymium oxide interlayer. Microelectronics Reliability 52(1): 147-150 (2012)
	2010
5		Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo: Dynamic voltage domain assignment technique for low power performance manageable cell based design. ASP-DAC 2010: 359-360
4		Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, Ching-Hwa Cheng: Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. ASP-DAC 2010: 367-368
	2007
3		Chien-Nan Liao, Feng-Tso Chien, Chi-Ling Wang, Hsien-Chin Chiu, Yi-Jen Chan: A Novel Power MOSFET Structure with Shallow Junction Dual Well Design. IEICE Transactions 90-C(5): 937-942 (2007)
	2006
2		Feng-Tso Chien, Chien-Nan Liao, Chi-Ling Wang, Hsien-Chin Chiu: High Performance Power MOSFETs by Wing-Cell Structure Design. IEICE Transactions 89-C(5): 591-595 (2006)
	2005
1		Feng-Tso Chien, Ming-Hung Lai, Shih-Tzung Su, Kou-Way Tu, Ching-Ling Cheng: High Ruggedness Power MOSFET Design by a Self-Align p+ Process. IEICE Transactions 88-C(4): 694-698 (2005)

Coauthor Index

1	Yi-Jen Chan	[3]
2	Shuo-Wen Chang	[4]
3	Chao-Hung Chen	[6]
4	Ching-Hwa Cheng	[4] [5]
5	Ching-Ling Cheng	[1]
6	Hsien-Chin Chiu	[2] [3] [6]
7	Chen-I Chung	[4]
8	Jeffrey S. Fu	[6]
9	Jiun-In Guo	[5]
10	Ming-Hung Lai	[1]
11	Elone Lee	[5]
12	Chien-Nan Liao	[2] [3]
13	Shih-Tzung Su	[1]
14	Kou-Way Tu	[1]
15	Chi-Ling Wang	[2] [3]
16	Chih-Wei Yang	[6]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page