 | 2009 |
|---|
| 10 |       | Cheng-An Chien,
Chih-Da Chien,
Jui-Chin Chu,
Jiun-In Guo,
Ching-Hwa Cheng:
A Multi-standard Video Decoder for High Definition Video Applications.
ISCAS 2009: 1933 |
| 9 | | Chih-Da Chien,
Cheng-An Chien,
Jui-Chin Chu,
Jiun-In Guo,
Ching-Hwa Cheng:
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications.
ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
| 2007 |
|---|
| 8 | | Chih-Da Chien,
Chih-Wei Wang,
Chiun-Chau Lin,
Tien-Wei Hsieh,
Yuan-Hwa Chu,
Jiun-In Guo:
A Low Latency Memory Controller for Video Coding Systems.
ICME 2007: 1211-1214 |
| 7 | | Guo-An Jian,
Chih-Da Chien,
Jiun-In Guo:
A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation.
ISCAS 2007: 1569-1572 |
| 2006 |
|---|
| 6 | | Chih-Da Chien,
Keng-Po Lu,
Yi-Hung Shih,
Jiun-In Guo:
A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications.
ISCAS 2006 |
| 2005 |
|---|
| 5 | | Chih-Da Chien,
Ho-Chun Chen,
Lin-Chieh Huang,
Jiun-In Guo:
A low-power motion compensation IP core design for MPEG-1/2/4 video decoding.
ISCAS (5) 2005: 4542-4545 |
| 2004 |
|---|
| 4 |  | Tai-Lun Chang,
Ying-Ming Tsai,
Chih-Da Chien,
Chien-Chang Lin,
Jiun-In Guo:
A high-performance MPEG4 bitstream processing core.
ICME 2004: 467-470 |
| 3 | | Chih-Da Chien,
Chien-Chang Lin,
Jiun-In Guo,
Tien-Fu Chen:
A power-aware IP core generator for the one-dimensional discrete Fourier transform.
ISCAS (3) 2004: 637-640 |
| 2003 |
|---|
| 2 | | Jiun-In Guo,
Chih-Da Chien,
Chien-Chang Lin:
A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining.
ISCAS (5) 2003: 293-296 |
| 2002 |
|---|
| 1 | | Jiun-In Guo,
Chien-Chang Lin,
Chih-Da Chien:
A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths.
Journal of Circuits, Systems, and Computers 11(4): 405-428 (2002) |
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