 | 2011 |
|---|
| 8 |       | Cheng-An Chien,
Yao-Chang Yang,
Hsiu-Cheng Chang,
Jia-Wei Chen,
Cheng-Yen Chang,
Jiun-In Guo,
Jinn-Shyan Wang,
Ching-Hwa Cheng:
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video.
ASP-DAC 2011: 73-74 |
| 7 | | Yu-Tzu Tsai,
Cheng-Chih Tsai,
Cheng-An Chien,
Ching-Hwa Cheng,
Jiun-In Guo:
Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism.
ASP-DAC 2011: 85-86 |
| 6 | | Yu-Tzu Tsai,
Cheng-Chih Tsai,
Cheng-An Chien,
Ching-Hwa Cheng,
Jiun-In Guo:
A low-power management technique for high-performance domino circuits.
ASP-DAC 2011: 93-94 |
| 2009 |
|---|
| 5 | | Hsiu-Cheng Chang,
Yao-Chang Yang,
Jia-Wei Chen,
Ching-Lung Su,
Cheng-An Chien,
Jiun-In Guo,
Jinn-Shyan Wang:
A dynamic quality-scalable H.264 video encoder chip.
ASP-DAC 2009: 125-126 |
| 4 | | Hsiu-Cheng Chang,
Jia-Wei Chen,
Yao-Chang Yang,
Cheng-An Chien,
Tzu-Chun Chang,
Jinn-Shyan Wang,
Jiun-In Guo:
A Dynamic Quality-scalable H.264 Video Encoder.
ISCAS 2009: 1932 |
| 3 | | Cheng-An Chien,
Chih-Da Chien,
Jui-Chin Chu,
Jiun-In Guo,
Ching-Hwa Cheng:
A Multi-standard Video Decoder for High Definition Video Applications.
ISCAS 2009: 1933 |
| 2 | | Cheng-An Chien,
Hsiu-Cheng Chang,
Jiun-In Guo:
A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards.
ISCAS 2009: 2377-2380 |
| 1 | | Chih-Da Chien,
Cheng-An Chien,
Jui-Chin Chu,
Jiun-In Guo,
Ching-Hwa Cheng:
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications.
ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
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