Vivek Chickermane

	2011
24		Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario H. Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel: Automation of 3D-DfT Insertion. Asian Test Symposium 2011: 395-400
	2010
23		Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise: Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC 2010: 724-733
	2009
22		Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman: Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. Asian Test Symposium 2009: 295-300
21		Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang: Capture power reduction using clock gating aware test generation. ITC 2009: 1-9
20		Krishna Chakravadhanula, Vivek Chickermane: Automating IEEE 1500 Core Test—An EDA Perspective. IEEE Design & Test of Computers 26(3): 6-15 (2009)
	2008
19		Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula: A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. ITC 2008: 1-10
	2005
18		Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi: Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium 2005: 156-161
17		Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman: Practical Aspects of Delay Testing for Nanometer Chips. Asian Test Symposium 2005: 470
	2004
16		Vivek Chickermane, Brian Foutz, Brion L. Keller: Channel Masking Synthesis for Efficient On-Chip Test Compression. ITC 2004: 452-461
15		Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane: An Economic Analysis and ROI Model for Nanometer Test. ITC 2004: 518-524
	2001
14		Patrick R. Gallagher Jr., Vivek Chickermane, Steven Gregor, Thomas S. Pierre: A building block BIST methodology for SOC designs: a case study. ITC 2001: 111-120
13		Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane: System-on-Chip Testability Using LSSD Scan Structures. IEEE Design & Test of Computers 18(3): 83-97 (2001)
	2000
12		Vivek Chickermane, Scott Richter, Carl Barnhart: Integrating Logic BIST in VLSI Designs with Embedded Memories. VTS 2000: 157-164
	1997
11		Vivek Chickermane, Kamran Zarrineh: Addressing Early Design-For-Test Synthesis in a Production Environment. ITC 1997: 246-255
	1996
10		Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer: A Design For Test Perspective on I/O Management. ICCD 1996: 46-
	1995
9		Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel: Sequential circuit testability enhancement using a nonscan approach. IEEE Trans. VLSI Syst. 3(2): 333-338 (1995)
	1994
8		Vivek Chickermane, Jaushin Lee, Janak H. Patel: Addressing design for testability at the architectural level. IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 920-934 (1994)
7		Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel: An observability enhancement approach for improved testability and at-speed test. IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1051-1056 (1994)
	1993
6		Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel: Non-Scan Design-for-Testability Techniques for Sequential Circuits. DAC 1993: 236-241
	1992
5		Sungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel: APT: An Area-Performance-Testability Driven Placement Algorithm. DAC 1992: 141-146
4		Vivek Chickermane, Jaushin Lee, Janak H. Patel: A comparative study of design for testability methods using high-level and gate-level descriptions. ICCAD 1992: 620-624
3		Vivek Chickermane, Jaushin Lee, Janak H. Patel: Design for Testability Using Architectural Descriptions. ITC 1992: 752-761
	1991
2		Vivek Chickermane, Janak H. Patel: A Fault Oriented Partial Scan Design Approach. ICCAD 1991: 400-403
	1990
1		Vivek Chickermane, Janak H. Patel: An optimization based approach to the partial scan design problem. ITC 1990: 377-386

Coauthor Index

1	Prithviraj Banerjee (Prith Banerjee)	[5] [6] [9]
2	Carl Barnhart	[12]
3	Thomas Bartenstein	[15]
4	Krishna Chakravadhanula	[19] [20] [21] [22] [23]
5	Sergej Deutsch	[24]
6	Brian Foutz	[16] [23]
7	Patrick R. Gallagher Jr.	[14] [19] [21] [22]
8	Sandeep Kumar Goel	[24]
9	Steven Gregor	[14]
10	Gary Grise	[23]
11	Vikram Iyengar	[23]
12	Brion L. Keller	[15] [16] [17] [18] [21] [22] [23] [24]
13	Sungho Kim	[5]
14	Mario H. Konijnenburg (M. H. Konijnenburg)	[24]
15	David E. Lackey	[23]
16	Jaushin Lee	[3] [4] [8]
17	R. Malneedi	[23]
18	Erik Jan Marinissen	[24]
19	Kevin McCauley	[17]
20	Subhasish Mukherjee	[24]
21	Hiroyuki Nakamura	[18]
22	Prashant Narang	[21]
23	Gareth Nicholls	[10]
24	Yoshihito Nishizaki	[18]
25	Mike Palmer	[10]
26	Janak H. Patel	[1] [2] [3] [4] [5] [6] [7] [8] [9]
27	Thomas S. Pierre	[14]
28	Scott Richter	[12]
29	Elizabeth M. Rudnick	[6] [7] [9]
30	James Sage	[19]
31	Akio Shirokane	[18]
32	Thomas J. Snethen	[23]
33	Mick Tegethoff	[15]
34	Yoshihiko Terauchi	[18]
35	Tsutomu Ube	[18]
36	Shambhu J. Upadhyaya	[13]
37	Anis Uzzaman	[17] [18] [22]
38	Paul Yuan	[19]
39	Kamran Zarrineh	[10] [11] [13]

Colors in the list of coauthors

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