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| 2012 | ||
|---|---|---|
| 34 | Chih-Hsien Hsia, Jing-Ming Guo, Jen-Shiun Chiang: A fast Discrete Wavelet Transform algorithm for visual processing applications. Signal Processing 92(1): 89-106 (2012) | |
| 2011 | ||
| 33 | Jen-Shiun Chiang, Chih-Hsien Hsia, Hung-Wei Hsu, Chun-I. Li: Stereo vision-based self-localization system for RoboCup. FUZZ-IEEE 2011: 2763-2770 | |
| 2009 | ||
| 32 | Chih-Hsien Hsia, Ding-Wei Huang, Jen-Shiun Chiang, Zong-Jheng Wu: Moving Object Tracking Using Symmetric Mask-Based Scheme. IAS 2009: 173-176 | |
| 31 | Jen-Shiun Chiang, Ting-Hao Hwang, Tsung-Ta Lin, Kuang-Che Teng: High Efficiency Architecture of ESCOT with Word-Level Pass Concurrent Context Modeling Scheme for SVC. ISCAS 2009: 1061-1064 | |
| 30 | Po-Sheng Chen, Hsin-Liang Chen, Jen-Shiun Chiang: Digital Compensated Methodology of a 2-1-1 Cascaded Continuous Time Delta-sigma Modulator. ISCAS 2009: 2245-2248 | |
| 29 | Wei-Ming Li, Chih-Hsien Hsia, Jen-Shiun Chiang: Memory-efficient Architecture of 2-D Dual-mode Discrete Wavelet Transform using Lifting Scheme for Motion-JPEG2000. ISCAS 2009: 750-753 | |
| 28 | Chih-Hsien Hsia, Jing-Ming Guo, Jen-Shiun Chiang, Chia-Hui Lin: A Novel Fast Algorithm based on SMDWT for Visual Processing Applications. ISCAS 2009: 762-765 | |
| 27 | Chih-Hsien Hsia, Jing-Ming Guo, Jen-Shiun Chiang: Improved Low-Complexity Algorithm for 2-D Integer Lifting-Based Discrete Wavelet Transform Using Symmetric Mask-Based Scheme. IEEE Trans. Circuits Syst. Video Techn. 19(8): 1202-1208 (2009) | |
| 26 | Hsin-Liang Chen, Po-Sheng Chen, Jen-Shiun Chiang: A Low-Offset Low-Noise Sigma-Delta Modulator With Pseudorandom Chopper-Stabilization Technique. IEEE Trans. on Circuits and Systems 56-I(12): 2533-2543 (2009) | |
| 2008 | ||
| 25 | Tsung-Ta Lin, Jen-Shiun Chiang: Low cost architecture for JPEG2000 encoder without code-block memory. ICME 2008: 137-140 | |
| 24 | Jen-Shiun Chiang, Ting-Hao Hwang, Tsung-Ta Lin, Chih-Hsien Hsia: High efficiency architecture of escot with pass concurrent context modeling scheme for scalable video coding. ISCAS 2008: 2801-2804 | |
| 2007 | ||
| 23 | Chih-Hsien Hsia, Jen-Shiun Chiang, Ying-Hong Wang, Tsai-Yuan: Fast Intra Prediction Mode Decision Algorithm for H.264/AVC Video Coding Standard. IIH-MSP 2007: 535-538 | |
| 22 | Hsin-Chuan Chen, Jen-Shiun Chiang: A High-Performance Sequential MRU Cache Using Valid-Bit Assistant Search Algorithm. Journal of Circuits, Systems, and Computers 16(4): 613-626 (2007) | |
| 2006 | ||
| 21 | Jen-Shiun Chiang, Yi-Tsung Li, Hsin-Liang Chen: A 20-MS/s sigma delta modulator for 802.11a applications. ISCAS 2006 | |
| 20 | Jen-Shiun Chiang, Chang-Yo Hsieh, Jin-Chan Liu, Cheng-Chih Chien: Concurrent bit-plane coding architecture for EBCOT in JPEG2000. ISCAS 2006 | |
| 19 | Jen-Shiun Chiang, Chun-Hau Chang, Chang-Yo Hsieh, Chih-Hsien Hsia: High Efficiency EBCOT with Parallel Coding Architecture for JPEG2000. EURASIP J. Adv. Sig. Proc. 2006: (2006) | |
| 2005 | ||
| 18 | Hsin-Chuan Chen, Jen-Shiun Chiang: Low-Power Way-Predicting Cache Using Valid-Bit Pre-Decision for Parallel Architectures. AINA 2005: 203-206 | |
| 17 | Jen-Shiun Chiang, Chih-Hsien Hsia, Hsin-Jung Chen: 2-D Discrete Wavelet Transform with Efficient Lifting-Based Scheme. CISST 2005: 193-197 | |
| 16 | Jen-Shiun Chiang, Sin-Guo Jhou, Yen-Jen Chen, Je-Yu Tzou: Temporal-Correlaction for Separating Block PSNR to Evaluate Video Coding Quality. CISST 2005: 20-26 | |
| 15 | Jen-Shiun Chiang, Chih-Hsien Hsia, Hsin-Jung Chen, Te-Jung Lo: VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications. ISCAS (5) 2005: 4554-4557 | |
| 2004 | ||
| 14 | Fun Ye, Jen-Shiun Chiang, Chun-Cheng Wu: Low Power Sigma-Delta Modulator with Dynamic Biasing for Speech CODECs. ESA/VLSI 2004: 31-35 | |
| 13 | Cheng-Chih Chien, Jen-Shiun Chiang, Ming-Hung Tu, Yu-Cheng Sung, Yi-Tsung Lee: Low-Power Switched-Capacitor Filters for Telecommunication Applications. ESA/VLSI 2004: 36-39 | |
| 12 | Jen-Shiun Chiang, Chun-Hau Chang, Yu-Sen Lin, Chang-You Hsieh, Chih-Hsieh Hsia: High-speed EBCOT with dual context-modeling coding architecture for JPEG2000. ISCAS (3) 2004: 865-868 | |
| 11 | Hsin-Chuan Chen, Jen-Shiun Chiang: A low-jitter phase-interpolation DDS using dual-slope integration. IEICE Electronic Express 1(12): 333-338 (2004) | |
| 2003 | ||
| 10 | Jen-Shiun Chiang, Ying-Hong Wang, Chih-Hsiao Tsai, Chih-Peng Hsu: Location Management and Multimedia Communication Service Based on Mobile IP and Cellular IP Network. AINA 2003: 223-228 | |
| 9 | Ying-Hong Wang, Chen-An Wang, Jen-Shiun Chiang, Wen-Hung Lo: A Secure Model in Agent-Based Marketplace. AINA 2003: 302-305 | |
| 8 | Jen-Shiun Chiang, Hsin-Liang Chen: A MASH Sigme-Delta Modulator with Low-Distortion Architecture. Embedded Systems and Applications 2003: 243-247 | |
| 7 | Jen-Shiun Chiang, Hsueh-Ping Chen, Cheng-ming Ying: A 1V 0.54µW fourth order switched capacitor filter with switched opamp technique for cardiac pacemaker sensing channel. ISCAS (1) 2003: 481-484 | |
| 6 | Jen-Shiun Chiang, Pao-Chu Chou, Teng-Hung Chang: Dual-mode sigma-delta modulator for wideband receiver applications. ISCAS (1) 2003: 997-1000 | |
| 5 | Jen-Shiun Chiang, Min-Shiou Tsai: A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling. VLSI Signal Processing 33(1-2): 117-124 (2003) | |
| 2002 | ||
| 4 | Jen-Shiun Chiang, Yu-Sen Lin, Chang-Yo Hsieh: Efficient pass-parallel architecture for EBCOT in JPEG2000. ISCAS (1) 2002: 773-776 | |
| 1999 | ||
| 3 | Jen-Shiun Chiang, Jian-Kao Chen: An efficient VLSI architecture for RSA public-key cryptosystem. ISCAS (1) 1999: 496-499 | |
| 1992 | ||
| 2 | Mi Lu, Jen-Shiun Chiang: A Novel Division Algorithm for the Residue Number System. IEEE Trans. Computers 41(8): 1026-1032 (1992) | |
| 1991 | ||
| 1 | Jen-Shiun Chiang, Mi Lu: A general division algorithm for residue number systems. IEEE Symposium on Computer Arithmetic 1991: 76-83 | |
Colors in the list of coauthors
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