 | 2012 |
|---|
| 7 |       | Ho-lin Chang,
Hsiang-Cheng Lai,
Tsu-Yun Hsueh,
Wei-Kai Cheng,
Mely Chen Chi:
A 3D IC designs partitioning algorithm with power consideration.
ISQED 2012: 137-142 |
| 2011 |
|---|
| 6 | | Tsu-Yun Hsueh,
Hsiang-Hui Yang,
Wei-Chieh Wu,
Mely Chen Chi:
A layer prediction method for minimum cost three dimensional integrated circuits.
ISQED 2011: 359-363 |
| 2010 |
|---|
| 5 | | Yu Cheng Hu,
Yin Lin Chung,
Mely Chen Chi:
A multilevel multilayer partitioning algorithm for three dimensional integrated circuits.
ISQED 2010: 483-487 |
| 2005 |
|---|
| 4 | | Chih-Jen Yen,
Wen-Yaw Chung,
Mely Chen Chi:
A Wide-Swing V_T-Referenced Circuit with Insensitivity to Device Mismatch.
VLSI Design 2005: 539-542 |
| 2004 |
|---|
| 3 | | Chih-Jen Yen,
Wen-Yaw Chung,
Mely Chen Chi:
A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique.
VLSI Design 2004: 681-684 |
| 2003 |
|---|
| 2 | | Chih-Jen Yen,
Mely Chen Chi,
Wen-Yaw Chung,
Shing-Hao Lee:
A 0.75-mW analog processor IC for wireless biosignal monitor.
ISLPED 2003: 443-448 |
| 2000 |
|---|
| 1 | | Mely Chen Chi,
Shih-Hsu Huang:
A Reliable Clock Tree Design Methodology for ASIC Designs.
ISQED 2000: 269-274 |
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