Remy Chevallier

	2010
4		Abdelrezzak Bara, Pirouz Bazargan-Sabet, Remy Chevallier, Dominique Ledu, Emmanuelle Encrenaz, Patricia Renault: Formal Verification of Timed VHDL Programs. FDL 2010: 80-85
	2009
3		Remy Chevallier, Emmanuelle Encrenaz-Tiphène, Laurent Fribourg, Weiwen Xu: Timed verification of the generic architecture of a memory circuit using parametric timed automata. Formal Methods in System Design 34(1): 59-81 (2009)
	2006
2		Remy Chevallier, Emmanuelle Encrenaz-Tiphène, Laurent Fribourg, Weiwen Xu: Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata. FORMATS 2006: 113-127
	2005
1		Ghiath Al Sammane, Dominique Borrione, Remy Chevallier: Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning. ACM Great Lakes Symposium on VLSI 2005: 260-263

Coauthor Index

1	Abdelrezzak Bara	[4]
2	Pirouz Bazargan-Sabet	[4]
3	Dominique Borrione	[1]
4	Emmanuelle Encrenaz-Tiphène (Emmanuelle Encrenaz)	[2] [3] [4]
5	Laurent Fribourg	[2] [3]
6	Dominique Ledu	[4]
7	Patricia Renault	[4]
8	Ghiath Al Sammane	[1]
9	Weiwen Xu	[2] [3]

Colors in the list of coauthors

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