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| 2011 | ||
|---|---|---|
| 17 | Chen-Yong Cher, Eren Kursun: Exploring the effects of on-chip thermal variation on high-performance multicore architectures. TACO 8(1): 2 (2011) | |
| 2010 | ||
| 16 | Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban: Power-efficient, reliable microprocessor architectures: modeling and design methods. ACM Great Lakes Symposium on VLSI 2010: 299-304 | |
| 15 | Alejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip Bose: Performance and power evaluation of an in-line accelerator. Conf. Computing Frontiers 2010: 81-82 | |
| 14 | Charles L. Johnson, David H. Allen, Jeffrey D. Brown, Steve Vanderwiel, Russ Hoover, Heather D. Achilles, Chen-Yong Cher, George A. May, Hubertus Franke, Jimi Xenedis, Claude Basso: A wire-speed powerTM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads. ISSCC 2010: 104-105 | |
| 13 | Victor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose: Power and thermal characterization of POWER6 system. PACT 2010: 7-18 | |
| 12 | Victor Jiménez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero: Trends and techniques for energy efficient architectures. VLSI-SoC 2010: 276-279 | |
| 2009 | ||
| 11 | Eren Kursun, Chen-Yong Cher: Temperature Variation Characterization and Thermal Management of Multicore Architectures. IEEE Micro 29(1): 116-126 (2009) | |
| 2008 | ||
| 10 | Eren Kursun, Chen-Yong Cher: Variation-aware thermal characterization and management of multi-core architectures. ICCD 2008: 280-285 | |
| 9 | Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero: Software-Controlled Priority Characterization of POWER5 Processor. ISCA 2008: 415-426 | |
| 8 | Chen-Yong Cher, Michael Gschwind: Cell GC: using the cell synergistic processor as a garbage collection coprocessor. VEE 2008: 141-150 | |
| 2007 | ||
| 7 | Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, Hendrik F. Hamann, Alan J. Weger, Pradip Bose: Thermal-aware task scheduling at the system software level. ISLPED 2007: 213-218 | |
| 2006 | ||
| 6 | Chen-Yong Cher, Il Park, T. N. Vijaykumar: Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?. ARCS 2006: 232-251 | |
| 5 | Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi: An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. MICRO 2006: 347-358 | |
| 2005 | ||
| 4 | Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar: Combined circuit and architectural level variable supply-voltage scaling for low power. IEEE Trans. VLSI Syst. 13(5): 564-576 (2005) | |
| 2004 | ||
| 3 | Chen-Yong Cher, Antony L. Hosking, T. N. Vijaykumar: Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign. ASPLOS 2004: 199-210 | |
| 2003 | ||
| 2 | Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy: VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. MICRO 2003: 19-28 | |
| 2001 | ||
| 1 | Chen-Yong Cher, T. N. Vijaykumar: Skipper: a microarchitecture for exploiting control-flow independence. MICRO 2001: 4-15 | |
Colors in the list of coauthors
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