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| 2001 | ||
|---|---|---|
| 1 | Chichyang Chen, Liang-An Chen, Jih-Ren Cheng: Architectural Design of a Fast Floating-Point Multiplication-Add Fused Unit Using Signed-Digit Addition. DSD 2001: 346-353 | |
| 1 | Chichyang Chen | [1] |
| 2 | Liang-An Chen | [1] |
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