Ching-Hwa Cheng

	2011
29		Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng: A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. ASP-DAC 2011: 73-74
28		Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo: Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. ASP-DAC 2011: 85-86
27		Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo: A low-power management technique for high-performance domino circuits. ASP-DAC 2011: 93-94
	2010
26		Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng: Built-in self at-speed delay binning and calibration mechanism in wireless test platform. ASP-DAC 2010: 357-358
25		Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo: Dynamic voltage domain assignment technique for low power performance manageable cell based design. ASP-DAC 2010: 359-360
24		Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, Ching-Hwa Cheng: Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. ASP-DAC 2010: 367-368
	2009
23		Ming-Chien Tsai, Ching-Hwa Cheng: A full-synthesizable high-precision built-in delay time measurement circuit. ASP-DAC 2009: 123-124
22		Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo: CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. ASP-DAC 2009: 93-94
21		Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li: Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test. Asian Test Symposium 2009: 163-168
20		Ching-Hwa Cheng, Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung: Design High-Performance and Low-Power Adder Cores with Full-Swing Nodes for Embedded Systems. IIH-MSP 2009: 534-537
19		Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng: A Multi-standard Video Decoder for High Definition Video Applications. ISCAS 2009: 1933
18		Chen-I Chung, Shuo-Wen Chang, Ching-Hwa Cheng: Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. ITC 2009: 1
17		Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng: A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. ACM Trans. Design Autom. Electr. Syst. 14(1): (2009)
16		Ching-Hwa Cheng, Chin-Hsien Wang: CKVdd: A Clock-Controlled Self-Stabilized Voltage Technique for Reducing Dynamic Power in CMOS Digital Circuits. IEICE Transactions 92-C(4): 391-400 (2009)
	2008
15		Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang: An All-Digital High-Precision Built-In Delay Time Measurement Circuit. VTS 2008: 249-254
	2007
14		Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang, Ching-Hwa Cheng: Noise-Aware Floorplanning for Fast Power Supply Network Design. ISCAS 2007: 2028-2031
13		Hsiang-Hui Huang, Ching-Hwa Cheng: Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. VTS 2007: 110-118
12		De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang, Ching-Hwa Cheng: Fixed-outline floorplanning using robust evolutionary search. Eng. Appl. of AI 20(6): 821-830 (2007)
	2003
11		Ching-Hwa Cheng: Design Scan Test Strategy for Single Phase Dynamic Circuits. DFT 2003: 199-
	2002
10		Ching-Hwa Cheng: Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits. DFT 2002: 147-158
	2001
9		Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang: Charge-sharing alleviation and detection for CMOS domino circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 266-280 (2001)
	2000
8		Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang: Novel techniques for improving testability analysis. Asian Test Symposium 2000: 392-397
7		Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang: Charge sharing fault analysis and testing for CMOS domino logic circuits. Asian Test Symposium 2000: 435-440
6		Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone: Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. DFT 2000: 329-337
5		Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang: Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. ICCAD 2000: 387-390
	1999
4		Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone: Charge Sharing Fault Detection for CMOS Domino Logic Circuits. DFT 1999: 77-85
	1997
3		Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng: A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors. IEEE Trans. Computers 46(12): 1363-1371 (1997)
	1995
2		Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen: An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. VLSI Design 1995: 349-354
	1994
1		Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou: An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors. EDCC 1994: 421-438

Coauthor Index

1	Cheng-Yen Chang	[29]
2	Hsiu-Cheng Chang	[29]
3	Shih-Chieh Chang	[4] [5] [6] [7] [8] [9]
4	Shuo-Wen Chang	[18] [24]
5	De-Sheng Chen	[12] [14]
6	Jia-Wei Chen	[29]
7	Jwu-E Chen	[2]
8	Yung-Yuan Chen	[1] [2] [3]
9	Cheng-An Chien	[17] [19] [27] [28] [29]
10	Chih-Da Chien	[17] [19]
11	Feng-Tso Chien	[24] [25]
12	Yung-Ci Chou	[1]
13	Jui-Chin Chu	[17] [19]
14	Chen-I Chung	[18] [21] [24] [26]
15	Jiun-In Guo	[17] [19] [22] [25] [27] [28] [29]
16	Hsiang-Hui Huang	[13]
17	Yu-Cherng Hung	[20]
18	Jyun-Sian Jhou	[21] [26]
19	Wen-Ben Jone	[4] [5] [6] [7] [9]
20	Tai-Wei Kung	[14]
21	Elone Lee	[25]
22	Shin-De Lee	[9]
23	Shin-De Li	[5]
24	Sih-Yan Li	[21]
25	Chang-Tzu Lin	[12] [14]
26	Shao-Hui Shieh	[20]
27	Yin-He Su	[8]
28	Cheng-Chih Tsai	[27] [28]
29	Ming-Chien Tsai	[15] [23]
30	Yu-Tzu Tsai	[27] [28]
31	Chiou-Kou Tung	[20]
32	Shambhu J. Upadhyaya	[3]
33	Chin-Hsien Wang	[16] [22]
34	Jinn-Shyan Wang	[4] [5] [6] [7] [9] [29]
35	Yiwen Wang	[12] [14]
36	Chiou-Mao Yang	[15]
37	Yao-Chang Yang	[29]

Colors in the list of coauthors

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