 | 2012 |
|---|
| 36 |       | Jin-Tai Yan,
Jun-Min Chung,
Zhi-Wei Chen:
Density-reduction-oriented layer assignment for rectangle escape routing.
ACM Great Lakes Symposium on VLSI 2012: 275-278 |
| 35 | | Jin-Tai Yan,
Ming-Chien Huang,
Zhi-Wei Chen:
Top-down-based symmetrical buffered clock routing.
ACM Great Lakes Symposium on VLSI 2012: 75-78 |
| 34 | | Jin-Tai Yan,
Zhi-Wei Chen:
New optimal layer assignment for bus-oriented escape routing.
Integration 45(3): 341-347 (2012) |
| 2011 |
|---|
| 33 | | Jin-Tai Yan,
Zhi-Wei Chen:
New optimal layer assignment for bus-oriented escape routing.
ACM Great Lakes Symposium on VLSI 2011: 205-210 |
| 32 | | Jin-Tai Yan,
Zhi-Wei Chen:
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance.
DATE 2011: 449-454 |
| 31 | | Zhi-Wei Chen,
Jin-Tai Yan:
Timing-constrained I/O buffer placement for flip-chip designs.
DATE 2011: 619-624 |
| 30 | | Chang-Shing Lee,
Mei-Hui Wang,
Zhi-Wei Chen,
Chin-Yuan Hsu,
Su-E. Kuo,
Hui-Ching Kuo,
Hui-Hua Cheng,
Akio Naito:
Genetic fuzzy markup language for diet application.
FUZZ-IEEE 2011: 1791-1798 |
| 29 | | Jin-Tai Yan,
Zhi-Wei Chen:
Pre-assignment RDL routing via extraction of maximal net sequence.
ICCD 2011: 65-70 |
| 28 | | Te-En Wei,
Zhi-Wei Chen,
Chin-Wei Tien,
Jain-Shing Wu,
Hahn-Ming Lee,
Albert B. Jeng:
RePEF - A system for Restoring Packed Executable File for malware analysis.
ICMLC 2011: 519-527 |
| 27 | | Jin-Tai Yan,
Zhi-Wei Chen:
Obstacle-aware length-matching bus routing.
ISPD 2011: 61-68 |
| 26 | | Jin-Tai Yan,
Tung-Yen Sung,
Zhi-Wei Chen:
Simultaneous escape routing based on routability-driven net ordering.
SoCC 2011: 81-86 |
| 2010 |
|---|
| 25 | | Jin-Tai Yan,
Zhi-Wei Chen:
Resource-constrained timing-driven link insertion for critical delay reduction.
ACM Great Lakes Symposium on VLSI 2010: 119-122 |
| 24 | | Jin-Tai Yan,
Chung-Wei Ke,
Zhi-Wei Chen:
Ordered escape routing via routability-driven pin assignment.
ACM Great Lakes Symposium on VLSI 2010: 417-422 |
| 23 | | Jin-Tai Yan,
Ming-Ching Jhong,
Zhi-Wei Chen:
Obstacle-aware longest path using rectangular pattern detouring in routing grids.
ASP-DAC 2010: 287-292 |
| 22 | | Jin-Tai Yan,
Zhi-Wei Chen:
Two-sided single-detour untangling for bus routing.
DAC 2010: 206-211 |
| 21 | | Mei-Hui Wang,
Chang-Shing Lee,
Zhi-Wei Chen,
Chi-Fang Lo,
Su-E. Kuo,
Hui-Ching Kuo,
Hui-Hua Cheng:
Property and application of fuzzy ontology for dietary assessment.
FUZZ-IEEE 2010: 1-8 |
| 20 | | Zhi-Wei Chen,
Jin-Tai Yan:
Routability-driven flip-flop merging process for clock power reduction.
ICCD 2010: 203-208 |
| 19 | | Ming-Hui Chu,
Yi-Wei Chen,
Yuan Kang,
Zhi-Wei Chen:
The research of sampling frequency for A DC servo motor speed control system based on neural networks.
ICNC 2010: 1401-1405 |
| 18 | | Jin-Tai Yan,
Zhi-Wei Chen:
Low-cost low-power bypassing-based multiplier design.
ISCAS 2010: 2338-2341 |
| 17 | | Zhi-Wei Chen,
Jin-Tai Yan:
Width-constrained wire sizing for non-tree interconnections.
ISCAS 2010: 2586-2589 |
| 16 | | Jin-Tai Yan,
Ke-Chyuan Chen,
Zhi-Wei Chen:
Routability-driven RDL routing with pin reassignment.
SoCC 2010: 133-138 |
| 15 | | Jin-Tai Yan,
Yu-Cheng Chang,
Zhi-Wei Chen:
Thermal via planning for temperature reduction in 3D ICs.
SoCC 2010: 392-395 |
| 14 | | Zhi-Wei Chen,
Cheng-Chin Chiang,
Zi-Tian Hsieh:
Extending 3D Lucas-Kanade tracking with adaptive templates for head pose estimation.
Mach. Vis. Appl. 21(6): 889-903 (2010) |
| 2009 |
|---|
| 13 | | Jin-Tai Yan,
Zhi-Wei Chen:
RDL pre-assignment routing for flip-chip designs.
ACM Great Lakes Symposium on VLSI 2009: 401-404 |
| 12 | | Jin-Tai Yan,
Zhi-Wei Chen:
Redundant wire insertion for yield improvement.
ACM Great Lakes Symposium on VLSI 2009: 409-412 |
| 11 | | Yuan-Ko Huang,
Zhi-Wei Chen,
Chiang Lee:
Continuous K-Nearest Neighbor Query over Moving Objects in Road Networks.
APWeb/WAIM 2009: 27-38 |
| 10 | | Jin-Tai Yan,
Zhi-Wei Chen:
IO connection assignment and RDL routing for flip-chip designs.
ASP-DAC 2009: 588-593 |
| 9 | | Zhi-Wei Chen,
Jin-Tai Yan,
Hsing-Lin Ko:
Accurate Transformation-based Timing Analysis for RC Non-tree Circuits.
ISCAS 2009: 2942-2945 |
| 8 | | Jin-Tai Yan,
Zhi-Wei Chen:
Low-power multiplier design with row and column bypassing.
SoCC 2009: 227-230 |
| 2007 |
|---|
| 7 | | Jin-Tai Yan,
Zhi-Wei Chen,
Ming-Yuen Wu:
Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity.
ISCAS 2007: 3395-3398 |
| 6 | | Jin-Tai Yan,
Zhi-Wei Chen,
Ming-Yuen Wu:
Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity.
SoCC 2007: 295-298 |
| 2006 |
|---|
| 5 | | Jin-Tai Yan,
Zhi-Wei Chen,
Chia-Wei Wu,
Ming-Yuen Wu:
Optimal Network Analysis in Hierarchical Power Quad-Grids.
APCCAS 2006: 1289-1292 |
| 4 | | Kuen-Cheng Chiang,
Zhi-Wei Chen,
Jean Jyh-Jiun Shann:
Design and implementation of a reconfigurable hardware for secure embedded systems.
ASIACCS 2006: 364 |
| 3 | | Zhi-Wei Chen,
Yu-Cheng Lin,
Cheng-Chin Chiang:
In this paper, an approach for deaf-people.
ICPR (2) 2006: 104-107 |
| 2005 |
|---|
| 2 | | Chin-Hao Hsu,
Zhi-Wei Chen,
Cheng-Chin Chiang:
Region-Based Color Correction of Images.
ICITA (1) 2005: 710-715 |
| 1 | | Yen-Jen Oyang,
Shien-Ching Hwang,
Yu-Yen Ou,
Chien-Yu Chen,
Zhi-Wei Chen:
Data classification with radial basis function networks based on a novel kernel density estimation algorithm.
IEEE Transactions on Neural Networks 16(1): 225-236 (2005) |
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