Yung-Yuan Chen

	2010
19		Yung-Yuan Chen, Kuen-Long Leu: Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment. Microprocessors and Microsystems - Embedded Hardware Design 34(1): 49-61 (2010)
	2009
18		Kuen-Long Leu, Chin-Long Wey, Jwu-E Chen, Yung-Yuan Chen: Robustness investigation of the FlexRay system. SIES 2009: 148-151
17		Yung-Yuan Chen, Chung-Hsien Hsu, Kuen-Long Leu: SoC-level risk assessment using FMEA approach in system design with SystemC. SIES 2009: 82-89
	2008
16		Hung-Chuan Lai, Shi-Jinn Horng, Yung-Yuan Chen: An Online Control Flow Check for VLIW Processor. PRDC 2008: 256-264
15		Kun-Chun Chang, Yi-Chinag Wang, Chung-Hsien Hsu, Kuen-Long Leu, Yung-Yuan Chen: System-Bus Fault Injection Framework in SystemC Design Platform. SSIRI 2008: 211-212
14		Yung-Yuan Chen, Shu-Hao Hsu, Kuen-Long Leu: An Estimation Model of Vulnerability for Embedded Microprocessors. SSIRI 2008: 224-225
	2006
13		Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin: Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors. CDES 2006: 196-202
12		Yung-Yuan Chen, Kuen-Long Leu, Chao-Sung Yeh: Fault-Tolerant VLIW Processor Design and Error Coverage Analysis. EUC 2006: 754-765
	2005
11		Yung-Yuan Chen: Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring. IEEE Trans. Computers 54(10): 1298-1313 (2005)
	2004
10		Yung-Yuan Chen, Kun-Feng Chen: Incorporating Signature-Monitoring Technique in VLIW Processors. DFT 2004: 395-402
	2003
9		Yung-Yuan Chen, Shi-Jinn Horng, Hung-Chuan Lai: An Integrated Fault-Tolerant Design Framework for VLIW Processors. DFT 2003: 555-562
	1999
8		Yung-Yuan Chen: Concurrent Detection of Processor Control Errors by Hybrid Signature Monitoring. EDCC 1999: 437-454
	1997
7		Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng: A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors. IEEE Trans. Computers 46(12): 1363-1371 (1997)
	1995
6		Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen: An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. VLSI Design 1995: 349-354
	1994
5		Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou: An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors. EDCC 1994: 421-438
4		Yung-Yuan Chen, Shambhu J. Upadhyaya: Modeling the Reliability of a Class of Fault-Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy. IEEE Trans. Computers 43(6): 737-748 (1994)
	1993
3		Yung-Yuan Chen, Shambhu J. Upadhyaya: Reliability, Reconfiguration, and Spare Allocation Issues in Binary-Tree Architectures Based on Multiple-Level Redundancy. IEEE Trans. Computers 42(6): 713-723 (1993)
2		Yung-Yuan Chen, Shambhu J. Upadhyaya: Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy. IEEE Trans. Computers 42(9): 1136-1141 (1993)
	1990
1		Yung-Yuan Chen, Shambhu J. Upadhyaya: An analysis of a reconfigurable binary tree architecture based on multiple-level redundancy. FTCS 1990: 192-199

Coauthor Index

1	Kun-Chun Chang	[15]
2	Jwu-E Chen	[6] [18]
3	Kun-Feng Chen	[10]
4	Ching-Hwa Cheng	[5] [6] [7]
5	Yung-Ci Chou	[5]
6	Shi-Jinn Horng	[9] [16]
7	Chung-Hsien Hsu	[15] [17]
8	Shu-Hao Hsu	[14]
9	Hung-Chuan Lai	[9] [16]
10	Kuen-Long Leu	[12] [13] [14] [15] [17] [18] [19]
11	Li-Wen Lin	[13]
12	Shambhu J. Upadhyaya	[1] [2] [3] [4] [7]
13	Yi-Chinag Wang	[15]
14	Chin-Long Wey	[18]
15	Chao-Sung Yeh	[12]

Colors in the list of coauthors

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