Yiran Chen

	2012
52		Yiran Chen, Yaojun Zhang, Peiyuan Wang: Probabilistic design in spintronic memory and logic circuit. ASP-DAC 2012: 323-328
51		Xiang Chen, Jian Zeng, Yiran Chen, Wei Zhang, Hai Li: Fine-grained dynamic voltage scaling on OLED display. ASP-DAC 2012: 807-812
50		Xiuyuan Bi, Chao Zhang, Hai Li, Yiran Chen, Robinson E. Pino: Spintronic memristor based temperature sensor design with CMOS current reference. DATE 2012: 1301-1306
49		Yaojun Zhang, Xiaobin Wang, Yong Li, Alex K. Jones, Yiran Chen: Asymmetry of MTJ switching and its implication to STT-RAM designs. DATE 2012: 1313-1318
48		Bo Zhao, Jun Yang, Youtao Zhang, Yiran Chen, Hai Li: Architecting a common-source-line array for bipolar non-volatile memory devices. DATE 2012: 1451-1454
47		Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang: A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme. J. Solid-State Circuits 47(2): 560-573 (2012)
	2011
46		Yiran Chen, Hai Li: Emerging sensing techniques for emerging memories. ASP-DAC 2011: 204-210
45		Miao Hu, Hai Li, Yiran Chen, Xiaobin Wang, Robinson E. Pino: Geometry variations analysis of TiO2 thin-film and spintronic memristors. ASP-DAC 2011: 25-30
44		Peiyuan Wang, Xiang Chen, Yiran Chen, Hai Helen Li, Seung H. Kang, Xiaochun Zhu, Wenqing Wu: A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis. CICC 2011: 1-4
43		Chun Jason Xue, Youtao Zhang, Yiran Chen, Guangyu Sun, J. Jianhua Yang, Hai Li: Emerging non-volatile memories: opportunities and challenges. CODES+ISSS 2011: 325-334
42		Yi-Chung Chen, Hai Li, Yiran Chen, Robinson E. Pino: 3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers. DATE 2011: 583-586
41		Yaojun Zhang, Xiaobin Wang, Yiran Chen: STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view. ICCAD 2011: 471-477
40		Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh: Processor caches with multi-level spin-transfer torque ram cells. ISLPED 2011: 73-78
39		Ping Zhou, Bo Zhao, Youtao Zhang, Jun Yang, Yiran Chen: MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement. PACT 2011: 207-208
38		Wei Xu, Hongbin Sun, Xiaobin Wang, Yiran Chen, Tong Zhang: Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM). IEEE Trans. VLSI Syst. 19(3): 483-493 (2011)
37		Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai Helen Li: Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation. IET Computers & Digital Techniques 5(3): 213-220 (2011)
36		Miao Hu, Hai Helen Li, Yiran Chen, Xiaobin Wang: Spintronic Memristor: Compact Model and Statistical Analysis. J. Low Power Electronics 7(2): 234-244 (2011)
	2010
35		Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie: Impact of process variations on emerging memristor. DAC 2010: 877-882
34		Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang: A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM). DATE 2010: 148-153
33		Xiaobin Wang, Yiran Chen: Spintronic memristor devices and application. DATE 2010: 667-672
32		Guangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li: A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. HPCA 2010: 1-12
31		Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang: Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement. ICCAD 2010: 432-437
30		Yuan Zhang, Jie Tang, Jimeng Sun, Yiran Chen, Jinghai Rao: MoodCast: Emotion Prediction via Dynamic Continuous Factor Graph Model. ICDM 2010: 1193-1198
29		Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang: Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM. ISLPED 2010: 1-6
28		Dimin Niu, Yiran Chen, Yuan Xie: Low-power dual-element memristor based memory design. ISLPED 2010: 25-30
27		Yiran Chen, Wei Tian, Hai Li, Xiaobin Wang, Wenzhong Zhu: Scalability of PCMO-based resistive switch device in DSM technologies. ISQED 2010: 327-332
26		Wei Xu, Tong Zhang, Yiran Chen: Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed. IEEE Trans. VLSI Syst. 18(1): 66-74 (2010)
25		Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy: Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Trans. VLSI Syst. 18(11): 1621-1624 (2010)
24		Yiran Chen, Xiaobin Wang, Hai Li, Haiwen Xi, Yuan Yan, Wenzhong Zhu: Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies. IEEE Trans. VLSI Syst. 18(12): 1724-1734 (2010)
	2009
23		Wei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang: Improving STT MRAM storage density through smaller-than-worst-case transistor sizing. DAC 2009: 87-90
22		Hai Li, Yiran Chen: An overview of non-volatile memory technology and the implication for tools and architectures. DATE 2009: 731-736
21		Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen: A novel architecture of the 3D stacked MRAM L2 cache for CMPs. HPCA 2009: 239-249
20		Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li: The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies. ICCD 2009: 268-274
19		Hai Li, Haiwen Xi, Yiran Chen, John Stricklin, Xiaobin Wang, Tong Zhang: Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration. ISVLSI 2009: 217-222
18		Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh: Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. IEEE Trans. VLSI Syst. 17(12): 1749-1752 (2009)
17		Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li: Tolerating process variations in large, set-associative caches: The buddy cache. TACO 6(2): (2009)
	2008
16		Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Helen Li, Yiran Chen: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. DAC 2008: 554-559
15		Wei Xu, Tong Zhang, Yiran Chen: Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin. ISCAS 2008: 1898-1901
14		Yiran Chen, Xiaobin Wang, Hai Li, Harry Liu, Dimitar V. Dimitrov: Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM). ISQED 2008: 684-690
	2007
13		Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li: VOSCH: Voltage scaled cache hierarchies. ICCD 2007: 496-503
12		Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh: Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. ISLPED 2007: 195-200
11		Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen: Statistical Timing Analysis Considering Spatial Correlations. ISQED 2007: 102-107
	2006
10		Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh: SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ASP-DAC 2006: 158-163
	2005
9		Wai-Ching Douglas Lam, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen: Statistical based link insertion for robust clock network design. ICCAD 2005: 588-591
8		Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh: Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. ISLPED 2005: 115-118
7		Dongku Kang, Yiran Chen, Kaushik Roy: Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis. ISQED 2005: 48-53
6		Yiran Chen, Kaushik Roy, Cheng-Kok Koh: Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Trans. VLSI Syst. 13(1): 75-85 (2005)
	2004
5		Yiran Chen, Kaushik Roy, Cheng-Kok Koh: Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. ASP-DAC 2004: 893-898
4		Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar: DCG: deterministic clock-gating for low-power microprocessor design. IEEE Trans. VLSI Syst. 12(3): 245-254 (2004)
	2003
3		Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy: Deterministic Clock Gating for Microprocessor Power Reduction. HPCA 2003: 113-122
2		Yiran Chen, Kaushik Roy, Cheng-Kok Koh: Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED 2003: 229-234
	2002
1		Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy: Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. DATE 2002: 931-935

Coauthor Index

1	Venkataramanan Balakrishnan	[1] [9] [11]
2	Swarup Bhunia	[3] [4]
3	Xiuyuan Bi	[50]
4	Xiang Chen	[44] [51]
5	Yi-Chung Chen	[42]
6	Yibo Chen	[32]
7	Dimitar V. Dimitrov	[14]
8	Xiangyu Dong	[16] [21] [37]
9	Miao Hu	[36] [45]
10	Jitesh Jain	[9]
11	Alex K. Jones	[49]
12	Yongsoo Joo	[32]
13	Dongku Kang	[7]
14	Seung H. Kang	[44]
15	Cheng-Kok Koh	[1] [2] [5] [6] [8] [9] [10] [11] [12] [13] [17] [18] [20] [25] [40]
16	Wai-Ching Douglas Lam	[9]
17	Hai Li	[3] [4] [8] [10] [12] [13] [14] [17] [18] [19] [20] [22] [24] [25] [27] [29] [31] [32] [34] [40] [42] [43] [45] [46] [47] [48] [50] [51]
18	Hai Helen Li	[16] [36] [37] [44]
19	Hong Li	[11]
20	Jian Li	[21]
21	Jing Li	[12] [25]
22	Yong Li	[49]
23	Harry Liu	[14]
24	Dimin Niu	[28] [32] [35]
25	Robinson E. Pino	[42] [45] [50]
26	Jinghai Rao	[30]
27	Kaushik Roy	[1] [2] [3] [4] [5] [6] [7] [8] [10] [18] [25]
28	John Stricklin	[19]
29	Guangyu Sun	[16] [21] [25] [32] [43]
30	Hongbin Sun	[38]
31	Jimeng Sun	[30]
32	Zhenyu Sun	[31]
33	Jie Tang	[30]
34	Wei Tian	[27]
35	T. N. Vijaykumar	[3] [4]
36	Peiyuan Wang	[44] [52]
37	Xiaobin Wang	[14] [19] [23] [24] [27] [29] [31] [33] [34] [36] [38] [41] [45] [47] [49]
38	Weng-Fai Wong	[13] [17] [20] [40]
39	Wenqing Wu	[44]
40	Xiaoxia Wu	[16] [37]
41	Haiwen Xi	[19] [24]
42	Yuan Xie	[16] [21] [25] [28] [32] [35] [37]
43	Cong Xu	[35]
44	Wei Xu	[15] [23] [26] [29] [34] [38] [47]
45	Chun Jason Xue (Chun Xue)	[43]
46	Yuan Yan	[24]
47	J. Jianhua Yang	[43]
48	Jun Yang	[39] [48]
49	Jian Zeng	[51]
50	Chao Zhang	[50]
51	Tong Zhang	[15] [19] [23] [26] [29] [34] [38] [47]
52	Wei Zhang	[51]
53	Yaojun Zhang	[41] [49] [52]
54	Youtao Zhang	[39] [43] [48]
55	Yuan Zhang	[30]
56	Bo Zhao	[39] [48]
57	Ping Zhou	[39]
58	Wenzhong Zhu	[24] [27] [29] [34] [47]
59	Xiaochun Zhu	[44]

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