Yi-Jung Chen

	2011
8		Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen: TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems. IEEE Trans. Computers 60(6): 767-782 (2011)
	2010
7		Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang: PM-COSYN: PE and memory co-synthesis for MPSoCs. DATE 2010: 1590-1595
	2009
6		Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang: An architectural co-synthesis algorithm for energy-aware Network-on-Chip design. Journal of Systems Architecture - Embedded Systems Design 55(5-6): 299-309 (2009)
	2007
5		Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen: Cache leakage control mechanism for hard real-time systems. CASES 2007: 248-256
4		Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su: An architectural co-synthesis algorithm for energy-aware network-on-chip design. SAC 2007: 680-684
3		Yi-Jung Chen, Dyi-Rong Duh, Yunghsiang Sam Han: Improved Modulo (2n+1) Multiplier for IDEA. J. Inf. Sci. Eng. 23(3): 911-923 (2007)
	2006
2		Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen: Branch Behavior Characterization for Multimedia Applications. Asia-Pacific Computer Systems Architecture Conference 2006: 523-530
	2004
1		Yi-Jung Chen, Dyi-Rong Duh, Yunghsiang S. Han: A New Modulo (2n+1) Multiplier for IDEA. Security and Management 2004: 318-324

Coauthor Index

1	Yen-Sheng Chang	[4] [6]
2	Jian-Jia Chen	[5] [8]
3	Jaw-Wei Chi	[5] [8]
4	Dyi-Rong Duh	[1] [3]
5	Yunghsiang Sam Han (Yunghsiang S. Han)	[1] [3]
6	Wei-Hsuan Hung	[4]
7	Alan P. Su	[4]
8	Po-Han Wang	[7]
9	Shun-Ying Wang	[2]
10	Chia-Lin Yang	[2] [4] [5] [6] [7] [8]

Colors in the list of coauthors

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