 | 2012 |
|---|
| 6 |       | Xiaoheng Chen,
Shu Lin,
Venkatesh Akella:
Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes.
IEEE Trans. on Circuits and Systems 59-I(1): 188-197 (2012) |
| 2011 |
|---|
| 5 | | Xiaoheng Chen,
Jingyu Kang,
Shu Lin,
Venkatesh Akella:
Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders.
IEEE Trans. on Circuits and Systems 58-I(1): 98-111 (2011) |
| 4 | | Xiaoheng Chen,
Jingyu Kang,
Shu Lin,
Venkatesh Akella:
Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes.
IEEE Trans. on Circuits and Systems 58-I(12): 2931-2943 (2011) |
| 3 | | Xiaoheng Chen,
Venkatesh Akella:
Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA.
TRETS 4(4): 37 (2011) |
| 2010 |
|---|
| 2 | | Xiaoheng Chen,
Shu Lin,
Venkatesh Akella:
QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders.
IEEE Trans. on Circuits and Systems 57-II(10): 782-786 (2010) |
| 2009 |
|---|
| 1 | | Xiaoheng Chen,
Jingyu Kang,
Shu Lin,
Venkatesh Akella:
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing.
DATE 2009: 1530-1535 |
Data released under the ODC-BY 1.0 license — See also our legal information page