Wen-Tsao Chen

	2011
5		Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu: SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration. J. Solid-State Circuits 46(8): 1893-1903 (2011)
	2010
4		Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu: SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration. CICC 2010: 1-4
	2009
3		Wenbo Liu, Yuchun Chang, Szukang Hsien, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu: A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization. ISSCC 2009: 82-83
2		Jri Lee, Huaide Wang, Wen-Tsao Chen, Yung-Pin Lee: Subharmonically injection-locked PLLs for ultra-low-noise clock generation. ISSCC 2009: 92-93
	2008
1		Chung-Wei Lin, Yung-Pin Lee, Wen-Tsao Chen: A 1.5 bit 5th order CT/DT delta sigma class D amplifier with power efficiency improvement. ISCAS 2008: 280-283

Coauthor Index

1	Yuchun Chang	[3]
2	Bo-Wei Chen	[3] [4] [5]
3	Yun Chiu	[3] [4] [5]
4	Szukang Hsien	[3] [4] [5]
5	Pingli Huang	[4] [5]
6	Jri Lee	[2]
7	Seung-Chul Lee	[4] [5]
8	Yung-Pin Lee	[1] [2] [3] [4] [5]
9	Chung-Wei Lin	[1]
10	Wenbo Liu	[3] [4] [5]
11	Victor Lu	[4] [5]
12	Gin-Kou Ma	[3] [4] [5]
13	Peiyuan Wan	[4] [5]
14	Huaide Wang	[2]
15	Tzu-Yi Yang	[3] [4] [5]

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