 | 2012 |
| 12 |  | Tai-You Lu,
Wei-Zen Chen:
A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System.
IEEE Trans. VLSI Syst. 20(5): 948-958 (2012) |
| 11 |  | Wei-Zen Chen,
Tai-You Lu,
Wei-Wen Ou,
Shun-Tien Chou,
Song-Yu Yang:
A 2.4 GHz Reference-Less Receiver for 1 Mbps QPSK Demodulation.
IEEE Trans. on Circuits and Systems 59-I(3): 505-514 (2012) |
| 2011 |
| 10 |  | Yi-Peng Weng,
Hung-Ming Chen,
Tung-Chieh Chen,
Po-Cheng Pan,
Chien-Hung Chen,
Wei-Zen Chen:
Fast analog layout prototyping for nanometer design migration.
ICCAD 2011: 517-522 |
| 9 |  | Shih-Hao Huang,
Wei-Zen Chen,
Yu-Wei Chang,
Yang-Tung Huang:
A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18- μħbox m CMOS Technology.
J. Solid-State Circuits 46(5): 1158-1169 (2011) |
| 2010 |
| 8 |  | Wei-Zen Chen,
Wei-Wen Ou,
Tai-You Lu,
Shun-Tien Chou,
Song-Yu Yang:
A 2.4 GHz reference-less wireless receiver for 1Mbps QPSK demodulation.
ISCAS 2010: 1627-1630 |
| 7 |  | Song-Yu Yang,
Wei-Zen Chen,
Tai-You Lu:
A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology.
J. Solid-State Circuits 45(3): 578-586 (2010) |
| 2009 |
| 6 |  | Shih-Hao Huang,
Wei-Zen Chen:
A 10-Gbps CMOS single chip optical receiver with 2-D meshed spatially-modulated light detector.
CICC 2009: 129-132 |
| 5 |  | Song-Yu Yang,
Wei-Zen Chen:
A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS.
ISSCC 2009: 90-91 |
| 4 |  | Wei-Zen Chen,
Ruei-Ming Gan,
Shih-Hao Huang:
A Single-Chip 2.5-Gb/s CMOS Burst-Mode Optical Receiver.
IEEE Trans. on Circuits and Systems 56-I(10): 2325-2331 (2009) |
| 2008 |
| 3 |  | Wei-Zen Chen,
Guan-Sheng Huang:
Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications.
IEEE Trans. on Circuits and Systems 55-I(6): 1495-1501 (2008) |
| 2007 |
| 2 |  | Wei-Zen Chen,
Da-Shin Lin:
A 90-dB Omega 10-Gb/s Optical Receiver Analog Front-End in a 0.18µm CMOS Technology.
IEEE Trans. VLSI Syst. 15(3): 358-365 (2007) |
| 2006 |
| 1 |  | Wei-Zen Chen,
Guan-Sheng Huang:
A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications.
ISCAS 2006 |